 Emil J. Tywoniak
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66b2fdc8e4
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write_smt2: ignore $input_port
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2026-09-18 17:37:03 +02:00 |
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Emil J. Tywoniak
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9d93aa275a
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tests: ignore $input_port and $connect in cell counts
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2026-09-18 17:37:03 +02:00 |
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Emil J. Tywoniak
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f925de7dc4
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techlibs, ffinit: signorm fixes
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2026-09-18 17:37:03 +02:00 |
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Emil J. Tywoniak
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df2ea7d788
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memory: declare blackbox ports for generated RAM cells
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2026-09-18 17:29:46 +02:00 |
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Emil J. Tywoniak
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b24fcf8566
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passes: leave signorm mode where the index cannot be maintained
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2026-09-18 17:29:46 +02:00 |
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Emil J. Tywoniak
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8fcc7dedc5
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opt_clean: rewrite with signorm
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2026-09-18 17:29:41 +02:00 |
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Emil J. Tywoniak
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c0733c3b0f
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WIP signorm something about keep wires and positionals NEEDS FIXING
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2026-09-18 17:28:49 +02:00 |
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Emil J. Tywoniak
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9c68fd56e3
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signorm: expose the index so passes can use it in place
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2026-09-18 17:28:45 +02:00 |
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Emil J. Tywoniak
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b021a76f1f
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opt_expr: ignore $input_port
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2026-09-18 17:27:47 +02:00 |
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Emil J. Tywoniak
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42cb58d61f
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tests: signorm fix
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2026-09-17 15:43:55 +02:00 |
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Emil J. Tywoniak
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d84f48c408
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signorm: safer indexing if broken invariant
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2026-09-17 15:43:55 +02:00 |
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Emil J. Tywoniak
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d3015b171d
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check: check bufnorm too
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2026-09-17 15:43:55 +02:00 |
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Emil J. Tywoniak
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e3e3dd6cf3
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check: check signorm indices and wires
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2026-09-17 15:43:55 +02:00 |
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Emil J. Tywoniak
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aef0396485
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rtlil: publish signorm fanout
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2026-09-17 15:43:55 +02:00 |
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Emil J. Tywoniak
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406abc294c
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opt_merge: newcelltypes
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2026-09-17 15:43:55 +02:00 |
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Emil J. Tywoniak
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749359be65
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opt_merge: factor out hashing code across incremental and parallel
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2026-09-17 15:43:55 +02:00 |
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Emil J. Tywoniak
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593fa7d705
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opt_expr: replace invert_map with signorm traversal
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2026-09-17 15:43:55 +02:00 |
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Emil J. Tywoniak
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71ed61c7da
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signorm: add timers
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2026-09-17 15:43:55 +02:00 |
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Emil J. Tywoniak
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9e0ef9c567
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rtlil_bufnorm: fix setup_driven_wires constant handling on unknown port direction
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2026-09-17 15:43:55 +02:00 |
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Emil J. Tywoniak
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0b36e00c9a
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check: fix memory bug in $connect
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2026-09-17 15:43:55 +02:00 |
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Emil J. Tywoniak
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72547a4fa0
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memory_bram: create blackboxes
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2026-09-17 15:43:55 +02:00 |
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Emil J. Tywoniak
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8917baea67
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Revert "intel: register bram celltypes"
This reverts commit 16785a7f75af3a9d7be9f6450edbb927ce873d4a.
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2026-09-17 15:43:55 +02:00 |
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Emil J. Tywoniak
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28926712d6
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Revert "tests: use memory -bram-register in tests/bram"
This reverts commit 24488a7011474080bcb99a91d38ae27b2c2d813c.
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2026-09-17 15:43:55 +02:00 |
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Emil J. Tywoniak
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0ba02c4a99
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Revert "memory: add -bram-register"
This reverts commit 2bc6ea7f37f5c239491e83a3a8672af8954550ab.
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2026-09-17 15:43:55 +02:00 |
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Emil J. Tywoniak
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f0617a774f
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Revert "memory_bram: add -register"
This reverts commit b4b5093a14e5dceded852c644e70bf6ff447bba3.
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2026-09-17 15:43:55 +02:00 |
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Emil J. Tywoniak
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0b326f7b78
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intel_alm: loosen tests
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2026-09-17 15:43:55 +02:00 |
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Emil J. Tywoniak
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3893ce6384
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gowin: loosen tests
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2026-09-17 15:43:55 +02:00 |
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Emil J. Tywoniak
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8f58903473
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flatten: disable signorm
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2026-09-17 15:43:55 +02:00 |
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Emil J. Tywoniak
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1efbd42dba
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ecp5: loosen tests
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2026-09-17 15:43:54 +02:00 |
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Emil J. Tywoniak
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31ff903639
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nexus: loosen tests
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2026-09-17 15:43:54 +02:00 |
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Emil J. Tywoniak
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987e7ef633
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xilinx_dsp: signorm compatibility
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2026-09-17 15:43:54 +02:00 |
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Emil J. Tywoniak
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27b0e2e914
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pmgen: hold sigmap pointer instead of owning it
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2026-09-17 15:43:54 +02:00 |
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Emil J. Tywoniak
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8bd30b2e14
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equiv_miter: don't copy $input_port
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2026-09-17 15:43:54 +02:00 |
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Emil J. Tywoniak
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8795515e9e
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rtlil_bufnorm: more xlog
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2026-09-17 15:43:54 +02:00 |
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Emil J. Tywoniak
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af9f1ccffb
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design: properly switch signorm mode when restoring saved designs
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2026-09-17 15:43:54 +02:00 |
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Emil J. Tywoniak
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f5e357dbf6
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equiv_make: don't copy $input_port
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2026-09-17 15:43:54 +02:00 |
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Emil J. Tywoniak
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32bc4c869c
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rtlil: fix cloneInto in signorm
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2026-09-17 15:43:54 +02:00 |
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Emil J. Tywoniak
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1c08281114
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rtlil: sigNormalize Module when added to Design in signorm mode
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2026-09-17 15:43:54 +02:00 |
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Emil J. Tywoniak
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6ab0147609
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rtlil_bufnorm: more xlog
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2026-09-17 15:43:54 +02:00 |
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Emil J. Tywoniak
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d48be905be
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intel: register bram celltypes
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2026-09-17 15:43:54 +02:00 |
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Emil J. Tywoniak
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35263298db
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rtlil_bufnorm: ignore timing info harder
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2026-09-17 15:43:54 +02:00 |
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Emil J. Tywoniak
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d2c99efa2a
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gowin: replace positional arguments in cells_sim.v with named
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2026-09-17 15:43:54 +02:00 |
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Emil J. Tywoniak
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b632f6dc3d
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Revert "techmap: call hierarchy on map files to determine port directions"
This reverts commit eabbf6d22527f386811c7b507f74f887a258b397.
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2026-09-17 15:43:54 +02:00 |
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Emil J. Tywoniak
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3ecb03eaa0
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hierarchy: tolerance for apparent recursive instances in techmap files
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2026-09-17 15:43:54 +02:00 |
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Emil J. Tywoniak
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9226f55d17
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techmap: call hierarchy on map files to determine port directions
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2026-09-17 15:43:54 +02:00 |
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Emil J. Tywoniak
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74118fa9d2
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tests: use memory -bram-register in tests/bram
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2026-09-17 15:43:54 +02:00 |
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Emil J. Tywoniak
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a02f731a2e
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memory: add -bram-register
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2026-09-17 15:43:54 +02:00 |
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Emil J. Tywoniak
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027f84c2e5
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memory_bram: add -register
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2026-09-17 15:43:54 +02:00 |
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Emil J. Tywoniak
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5b0023b476
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ffmerge: initvals signorm compatibility fixup
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2026-09-17 15:43:54 +02:00 |
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Emil J. Tywoniak
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1336ca079e
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timinginfo: special-case $specify2 in signorm invariant
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2026-09-17 15:43:54 +02:00 |
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