luke
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Count module output ports as consumers.

This commit is contained in:
nella 2026-08-12 10:00:30 +02:00
parent bf86dd7faf
commit 7f5b7aacb9
3 changed files with 8 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
techlibs/gatemate/gatemate_foldinv.cc
View File

@ -125,6 +125,10 @@ struct FoldInvWorker {
void fold_output_inverters()
{
pool<SigBit> used_bits;
for (auto wire : module->wires())
if (wire->port_output)
for (auto bit : sigmap(SigSpec(wire)))
used_bits.insert(bit);
// Find bits that are actually used
for (auto cell : module->selected_cells()) {
for (auto conn : cell->connections()) {

4
tests/arch/gatemate/logic.ys
View File

@ -27,7 +27,7 @@ design -load orig
equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree -abc_new # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 4 t:CC_LUT1
select -assert-count 3 t:CC_LUT2
select -assert-count 1 t:CC_LUT1
select -assert-count 6 t:CC_LUT2
select -assert-count 2 t:CC_L2T4
select -assert-none t:CC_LUT1 t:CC_LUT2 t:CC_L2T4 %% t:* %D

4
tests/arch/gatemate/luttrees.ys
View File

@ -30,5 +30,5 @@ equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopa
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd luttrees # Constrain all select calls below inside the top module
select -assert-count 917 t:CC_LUT1 t:CC_LUT2 t:CC_L2T4 t:CC_L2T5 %%
select -assert-none t:CC_LUT1 t:CC_LUT2 t:CC_L2T4 t:CC_L2T5 %% t:* %D
select -assert-count 750 t:CC_LUT2 t:CC_L2T4 t:CC_L2T5 %%
select -assert-none t:CC_LUT2 t:CC_L2T4 t:CC_L2T5 %% t:* %D