mirror of https://github.com/YosysHQ/yosys.git
synth_lattice: remove classic ABC mapping
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Lofty
parent
dd4b6689e8
commit
ee75cd3ea0
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@ -104,10 +104,7 @@ struct SynthLatticePass : public ScriptPass
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log(" do not flatten design before synthesis\n");
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log("\n");
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log(" -dff\n");
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log(" run 'abc'/'abc9' with -dff option\n");
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log("\n");
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log(" -retime\n");
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log(" run 'abc' with '-dff -D 1' options\n");
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log(" run 'abc9' with -dff option\n");
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log("\n");
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log(" -noccu2\n");
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log(" do not use CCU2 cells in output netlist\n");
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@ -131,12 +128,6 @@ struct SynthLatticePass : public ScriptPass
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log(" -asyncprld\n");
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log(" use async PRLD mode to implement ALDFF (EXPERIMENTAL)\n");
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log("\n");
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log(" -abc2\n");
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log(" run two passes of 'abc' for slightly improved logic density\n");
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log("\n");
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log(" -noabc9\n");
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log(" disable use of new ABC9 flow\n");
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log("\n");
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log(" -iopad\n");
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log(" insert IO buffers\n");
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log(" (by default enabled on Nexus FPGAs)\n");
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@ -170,9 +161,9 @@ struct SynthLatticePass : public ScriptPass
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}
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string top_opt, edif_file, json_file, family, latches;
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bool noccu2, nodffe, nobram, nolutram, nowidelut, asyncprld, flatten, dff, retime, abc2, abc9, iopad, nodsp, no_rw_check, have_dsp;
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bool noccu2, nodffe, nobram, nolutram, nowidelut, asyncprld, flatten, dff, iopad, nodsp, no_rw_check, have_dsp;
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bool cmp2softlogic;
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string postfix, arith_map, brams_map, dsp_map, cells_map, map_ram_default, widelut_abc;
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string postfix, arith_map, brams_map, dsp_map, cells_map, map_ram_default;
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bool is_nexus;
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std::vector<DSPRule> dsp_rules;
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@ -190,9 +181,6 @@ struct SynthLatticePass : public ScriptPass
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asyncprld = false;
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flatten = true;
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dff = false;
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retime = false;
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abc2 = false;
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abc9 = true;
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iopad = false;
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nodsp = false;
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no_rw_check = false;
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@ -206,13 +194,11 @@ struct SynthLatticePass : public ScriptPass
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is_nexus = false;
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map_ram_default = "";
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cells_map = "";
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widelut_abc = "4:7";
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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string run_from, run_to;
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bool force_abc9 = false;
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bool force_widelut = false;
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bool force_iopad = false;
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clear_flags();
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@ -257,7 +243,7 @@ struct SynthLatticePass : public ScriptPass
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continue;
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}
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if (args[argidx] == "-retime") {
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retime = true;
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// Removed: ABC9 does not support retiming.
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continue;
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}
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if (args[argidx] == "-noccu2") {
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@ -291,17 +277,15 @@ struct SynthLatticePass : public ScriptPass
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continue;
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}
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if (args[argidx] == "-abc2") {
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abc2 = true;
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// Removed
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continue;
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}
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if (args[argidx] == "-abc9") {
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// removed, ABC9 is on by default.
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force_abc9 = true;
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// Removed: ABC9 is on by default.
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continue;
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}
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if (args[argidx] == "-noabc9") {
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force_abc9 = true;
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abc9 = false;
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// Removed: ABC9 is on by default.
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continue;
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}
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if (args[argidx] == "-iopad") {
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@ -358,7 +342,6 @@ struct SynthLatticePass : public ScriptPass
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cells_map = "_trellis";
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have_dsp = false;
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if (!force_widelut) nowidelut = true;
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if (!force_abc9) abc9 = false;
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} else if (family == "lifcl" ||
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family == "lfd2nx") {
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is_nexus = true;
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@ -370,9 +353,7 @@ struct SynthLatticePass : public ScriptPass
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have_dsp = true;
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map_ram_default = " -no-auto-huge";
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cells_map = "_nexus";
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widelut_abc = "4:5";
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if (!force_iopad) iopad = true;
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if (!force_abc9) abc9 = false;
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/* } else if (family == "xo" ||
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family == "pm") {
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} else if (family == "xp" ||
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@ -389,9 +370,6 @@ struct SynthLatticePass : public ScriptPass
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if (!design->full_selection())
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log_cmd_error("This command only operates on fully selected designs!\n");
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if (abc9 && retime)
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log_cmd_error("-retime option not currently compatible with -abc9!\n");
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log_header(design, "Executing SYNTH_LATTICE pass.\n");
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log_push();
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@ -500,8 +478,6 @@ struct SynthLatticePass : public ScriptPass
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run("attrmvcp -attr src -attr LOC -driven t:IB %x:+[I]");
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}
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run("opt -fast");
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if (retime || help_mode)
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run("abc -dff -D 1", "(only if -retime)");
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}
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if (check_label("map_ffs"))
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@ -532,8 +508,8 @@ struct SynthLatticePass : public ScriptPass
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run("dfflegalize" + dfflegalize_args, "($_*DFFE_* only if not -nodffe)");
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}
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run("opt_merge");
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if ((abc9 && dff) || help_mode)
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run("zinit -all w:* t:$_DFF_?_ t:$_DFFE_??_ t:$_SDFF*", "(only if -abc9 and -dff)");
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if (dff || help_mode)
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run("zinit -all w:* t:$_DFF_?_ t:$_DFFE_??_ t:$_SDFF*", "(only if -dff)");
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run("techmap -D NO_LUT -map +/lattice/cells_map" + cells_map + ".v");
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run("opt_expr -undriven -mux_undef");
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run("simplemap");
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@ -544,38 +520,23 @@ struct SynthLatticePass : public ScriptPass
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if (check_label("map_luts"))
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{
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if (abc2 || help_mode)
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run("abc", " (only if -abc2)");
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if (!asyncprld || help_mode) {
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if (latches == "error" || help_mode)
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run("check -latchonly -assert", "(skip if -asyncprld; only if -latches error, the default)");
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run("techmap -map +/lattice/latches_map.v", "(skip if -asyncprld)");
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}
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if (abc9) {
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std::string abc9_opts;
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if (nowidelut)
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abc9_opts += " -maxlut 4";
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std::string k = "synth_lattice.abc9.W";
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if (active_design && active_design->scratchpad.count(k))
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abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k));
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else
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abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k));
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if (nowidelut)
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abc9_opts += " -maxlut 4";
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if (dff)
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abc9_opts += " -dff";
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run("abc9" + abc9_opts);
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} else {
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std::string abc_args = " -dress";
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if (nowidelut)
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abc_args += " -lut 4";
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else
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abc_args += " -lut " + widelut_abc;
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if (dff)
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abc_args += " -dff";
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run("abc" + abc_args);
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}
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std::string abc9_opts;
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std::string k = "synth_lattice.abc9.W";
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if (active_design && active_design->scratchpad.count(k))
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abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k));
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else
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abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k));
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if (nowidelut)
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abc9_opts += " -maxlut 4";
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if (dff)
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abc9_opts += " -dff";
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run("abc9" + abc9_opts);
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run("clean");
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}
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@ -11,7 +11,7 @@ sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs mite
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design -load postopt
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cd lutram_1w1r
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select -assert-count 20 t:LUT4
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select -assert-count 28 t:LUT4
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select -assert-count 8 t:TRELLIS_DPR16X4
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select -assert-count 8 t:TRELLIS_FF
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select -assert-none t:LUT4 t:TRELLIS_DPR16X4 t:TRELLIS_FF %% t:* %D
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@ -15,7 +15,7 @@ proc
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equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux4 # Constrain all select calls below inside the top module
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select -assert-count 2 t:LUT4
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select -assert-count 3 t:LUT4
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select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D
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@ -25,7 +25,7 @@ proc
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equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux8 # Constrain all select calls below inside the top module
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select -assert-count 5 t:LUT4
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select -assert-count 6 t:LUT4
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select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D
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@ -35,6 +35,6 @@ proc
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equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux16 # Constrain all select calls below inside the top module
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select -assert-max 12 t:LUT4
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select -assert-max 13 t:LUT4
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select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D
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@ -1,21 +1,11 @@
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read_verilog ../common/add_sub.v
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hierarchy -top top
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proc
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design -save orig
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equiv_opt -assert -map +/nexus/cells_sim.v synth_nexus # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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stat
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select -assert-count 10 t:LUT4
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select -assert-none t:IB t:OB t:VLO t:LUT4 %% t:* %D
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design -load orig
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equiv_opt -assert -map +/nexus/cells_sim.v synth_nexus -abc9 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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stat
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select -assert-count 6 t:LUT4
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select -assert-count 4 t:WIDEFN9
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select -assert-none t:IB t:OB t:VLO t:LUT4 t:WIDEFN9 %% t:* %D
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@ -6,6 +6,7 @@ equiv_opt -assert -multiclock -map +/nexus/cells_sim.v synth_nexus # equivalency
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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stat
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select -assert-count 1 t:INV
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select -assert-count 5 t:CCU2
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select -assert-count 8 t:FD1P3DX
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select -assert-none t:CCU2 t:FD1P3DX t:IB t:OB t:VLO t:VHI %% t:* %D
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select -assert-none t:INV t:CCU2 t:FD1P3DX t:IB t:OB t:VLO t:VHI %% t:* %D
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@ -4,5 +4,5 @@ proc
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equiv_opt -assert -map +/nexus/cells_sim.v synth_nexus # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 8 t:LUT4
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select -assert-count 5 t:LUT4
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select -assert-none t:LUT4 t:INV t:IB t:OB t:VLO t:VHI %% t:* %D
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