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CMake: add missing dependency edges for `synth_*` passes.

This commit is contained in:
Catherine 2026-08-06 14:48:56 +00:00
parent 25b06f428e
commit 1277640bdf
14 changed files with 15 additions and 1 deletions
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2
frontends/aiger/CMakeLists.txt
View File

@ -1,4 +1,4 @@
yosys_frontend(aigerparse
yosys_frontend(aiger
aigerparse.cc
aigerparse.h
REQUIRES

2
passes/techmap/CMakeLists.txt
View File

@ -83,6 +83,7 @@ yosys_pass(abc9
design
opt
portarcs
read_aiger
read_verilog
scc
select
@ -90,6 +91,7 @@ yosys_pass(abc9
submod
techmap
wbflip
write_xaiger
)
yosys_pass(abc_new
abc_new.cc

1
techlibs/analogdevices/CMakeLists.txt
View File

@ -33,6 +33,7 @@ yosys_pass(synth_analogdevices
share
simplemap
stat
synth
techmap
tribuf
wreduce

1
techlibs/fabulous/CMakeLists.txt
View File

@ -22,6 +22,7 @@ yosys_pass(synth_fabulous
read_verilog
share
stat
synth
techmap
tribuf
wreduce

1
techlibs/gatemate/CMakeLists.txt
View File

@ -40,6 +40,7 @@ yosys_pass(synth_gatemate
share
simplemap
stat
synth
techmap
tribuf
wreduce

1
techlibs/gowin/CMakeLists.txt
View File

@ -31,6 +31,7 @@ yosys_pass(synth_gowin
sort
splitnets
stat
synth
techmap
tribuf
wreduce

1
techlibs/ice40/CMakeLists.txt
View File

@ -60,6 +60,7 @@ yosys_pass(synth_ice40
share
simplemap
stat
synth
techmap
tribuf
wreduce

1
techlibs/intel/CMakeLists.txt
View File

@ -24,6 +24,7 @@ yosys_pass(synth_intel
read_verilog
setundef
stat
synth
techmap
tribuf
wreduce

1
techlibs/intel_alm/CMakeLists.txt
View File

@ -25,6 +25,7 @@ yosys_pass(synth_intel_alm
read_verilog
share
stat
synth
techmap
tribuf
wreduce

1
techlibs/lattice/CMakeLists.txt
View File

@ -44,6 +44,7 @@ yosys_pass(synth_lattice
share
simplemap
stat
synth
techmap
tribuf
wreduce

1
techlibs/microchip/CMakeLists.txt
View File

@ -53,6 +53,7 @@ yosys_pass(synth_microchip
share
simplemap
stat
synth
techmap
tribuf
wreduce

1
techlibs/nanoxplore/CMakeLists.txt
View File

@ -31,6 +31,7 @@ yosys_pass(synth_nanoxplore
setundef
share
stat
synth
techmap
tribuf
wreduce

1
techlibs/quicklogic/CMakeLists.txt
View File

@ -68,6 +68,7 @@ yosys_pass(synth_quicklogic
share
shregmap
stat
synth
techmap
tribuf
wreduce

1
techlibs/xilinx/CMakeLists.txt
View File

@ -65,6 +65,7 @@ yosys_pass(synth_xilinx
simplemap
sort
stat
synth
techmap
tribuf
wreduce