CMake: add missing dependency edges for synth_* passes.

2026-10-06 10:03:36 +02:00 · 2026-08-06 14:48:56 +00:00
parent 25b06f428e
commit 1277640bdf
14 changed files with 15 additions and 1 deletions
@@ -1,4 +1,4 @@
-yosys_frontend(aigerparse
+yosys_frontend(aiger
 	aigerparse.cc
 	aigerparse.h
 	REQUIRES
@@ -83,6 +83,7 @@ yosys_pass(abc9
 		design
 		opt
 		portarcs
+		read_aiger
 		read_verilog
 		scc
 		select
@@ -90,6 +91,7 @@ yosys_pass(abc9
 		submod
 		techmap
 		wbflip
+		write_xaiger
 )
 yosys_pass(abc_new
 	abc_new.cc
@@ -33,6 +33,7 @@ yosys_pass(synth_analogdevices
 		share
 		simplemap
 		stat
+		synth
 		techmap
 		tribuf
 		wreduce
@@ -22,6 +22,7 @@ yosys_pass(synth_fabulous
 		read_verilog
 		share
 		stat
+		synth
 		techmap
 		tribuf
 		wreduce
@@ -40,6 +40,7 @@ yosys_pass(synth_gatemate
 		share
 		simplemap
 		stat
+		synth
 		techmap
 		tribuf
 		wreduce
@@ -31,6 +31,7 @@ yosys_pass(synth_gowin
 		sort
 		splitnets
 		stat
+		synth
 		techmap
 		tribuf
 		wreduce
@@ -60,6 +60,7 @@ yosys_pass(synth_ice40
 		share
 		simplemap
 		stat
+		synth
 		techmap
 		tribuf
 		wreduce
@@ -24,6 +24,7 @@ yosys_pass(synth_intel
 		read_verilog
 		setundef
 		stat
+		synth
 		techmap
 		tribuf
 		wreduce
@@ -25,6 +25,7 @@ yosys_pass(synth_intel_alm
 		read_verilog
 		share
 		stat
+		synth
 		techmap
 		tribuf
 		wreduce
@@ -44,6 +44,7 @@ yosys_pass(synth_lattice
 		share
 		simplemap
 		stat
+		synth
 		techmap
 		tribuf
 		wreduce
@@ -53,6 +53,7 @@ yosys_pass(synth_microchip
 		share
 		simplemap
 		stat
+		synth
 		techmap
 		tribuf
 		wreduce
@@ -31,6 +31,7 @@ yosys_pass(synth_nanoxplore
 		setundef
 		share
 		stat
+		synth
 		techmap
 		tribuf
 		wreduce
@@ -68,6 +68,7 @@ yosys_pass(synth_quicklogic
 		share
 		shregmap
 		stat
+		synth
 		techmap
 		tribuf
 		wreduce
@@ -65,6 +65,7 @@ yosys_pass(synth_xilinx
 		simplemap
 		sort
 		stat
+		synth
 		techmap
 		tribuf
 		wreduce