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17,307 Commits 135 Branches 69 Tags 48 MiB
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17307 Commits

Author SHA1 Message Date
Emil J. Tywoniak 61b0dfd3bf patch: gc collects src from every removed cell; ff.cc routes through Patch 2026-06-10 14:53:28 +02:00
Emil J. Tywoniak e583da906d patch: merge src into existing cells; opt_merge/_inc + onehot + ff.cc use Patch 2026-06-10 14:53:19 +02:00
Emil J. Tywoniak ea41e61a36 utils: add BitGrouper for shared bit-partition logic 2026-06-10 14:53:13 +02:00
Emil J. Tywoniak d952b04e54 opt_expr: convert remaining rewrites to patcher 2026-06-10 14:53:05 +02:00
Emil J. Tywoniak a689cdc6ed patch: don't track root cell deletions for perf 2026-06-10 14:53:04 +02:00
Emil J. Tywoniak e2a77db87a opt_expr: evener morer patcherer 2026-06-10 14:53:03 +02:00
Emil J. Tywoniak edeb649154 opt_expr: even more patcher 2026-06-10 14:53:02 +02:00
Emil J. Tywoniak f18f46cc9b patch: don't gc signorm cells 2026-06-10 14:53:01 +02:00
Emil J. Tywoniak fb021b1a6b opt_expr: more patcher again 2026-06-10 14:53:00 +02:00
Emil J. Tywoniak 48a3b84e88 WIP 2026-06-10 14:52:59 +02:00
Emil J. Tywoniak 1291cddcb1 WIP 2026-06-10 14:52:58 +02:00
Emil J. Tywoniak c264649ae7 rtlil, patch: incremental signorm via connect_incremental, replacing batched sigNormalize in Patch::patch 2026-06-10 14:52:53 +02:00
Emil J. Tywoniak c3457e2e5c WIP 2026-06-10 14:52:50 +02:00
Emil J. Tywoniak dab9a386cc opt_expr: WIP use patcher more 2026-05-28 22:51:30 +02:00
Emil J. Tywoniak b594196a48 opt_expr: cleanup 2026-05-28 14:56:27 +02:00
Emil J. Tywoniak 5cdb189ea0 opt_expr: cleanup 2026-05-28 14:53:21 +02:00
Emil J. Tywoniak 12e94a9a8c patch: cleanup 2026-05-28 14:49:07 +02:00
Emil J. Tywoniak cef8186c4a patch: infer leaves for gc 2026-05-28 12:56:13 +02:00
Emil J. Tywoniak 1cd0d37511 patch: instead of cell->cell, use port->sig rewrites 2026-05-27 18:07:01 +02:00
Emil J. Tywoniak b3a33aeeba opt_expr: use patcher for xor constant folding 2026-05-27 18:06:55 +02:00
Emil J. Tywoniak 688d256edc patch: fix gc 2026-05-27 17:04:31 +02:00
Emil J. Tywoniak 698f6e05c0 patch: fix const handling 2026-05-27 17:04:31 +02:00
Emil J. Tywoniak 5a6568edbe rtlil, patch: update signorm index and driver fields when committing Cell from Patch to Design 2026-05-23 01:09:26 +02:00
Emil J. Tywoniak b0eb50be1b fixup! patch: working multi-cell signorm invariant 2026-05-23 00:11:16 +02:00
Emil J. Tywoniak 9f22b9d2a0 patch: source transfer 2026-05-23 00:10:02 +02:00
Emil J. Tywoniak db1c1d4359 patch: working multi-cell signorm invariant 2026-05-23 00:10:00 +02:00
Emil J. Tywoniak e78e19acfe patch: fix patch mixins 2026-05-23 00:09:17 +02:00
Emil J. Tywoniak 8c26ecd2a6 patch: WIP multicell patch test 2026-05-23 00:09:17 +02:00
Emil J. Tywoniak 6b16a0cac8 patch: wires 2026-05-23 00:09:17 +02:00
Emil J. Tywoniak d2ae9b48e4 patch: signorm, move 2026-05-23 00:09:17 +02:00
Emil J. Tywoniak b7ea32dbee patch: unique heap 2026-05-23 00:09:17 +02:00
Emil J. Tywoniak dbc7e33908 rtlil: add CellAdderMixin for shared Cell adder interface between Module and Patch 2026-05-23 00:09:14 +02:00
Emil J. Tywoniak 770d74cc9b patch: GC comment 2026-05-23 00:07:39 +02:00
Emil J. Tywoniak 89e5c4ccca test_patch total basics 2026-05-23 00:07:39 +02:00
Emil J. Tywoniak 6f0be1b4e9 rtlil: allow friends to use Wire constructors with a factory token pattern 2026-05-23 00:07:39 +02:00
Emil J. Tywoniak 3e6b740430 rtlil: allow friends to use Cell constructors with a factory token pattern 2026-05-23 00:07:39 +02:00
Emil J. Tywoniak b3f605e0d2 patcher: start 2026-05-23 00:07:39 +02:00
Emil J. Tywoniak 25344b3947 Revert "tests: use memory -bram-register in tests/bram" 
This reverts commit 24488a7011474080bcb99a91d38ae27b2c2d813c.
 2026-05-23 00:05:51 +02:00
Emil J. Tywoniak 56461158b4 tests: use memory -bram-register in tests/bram 2026-05-23 00:05:32 +02:00
Emil J. Tywoniak 849526491a fixup! tests: signorm fix 2026-05-22 21:23:38 +02:00
Emil J. Tywoniak 54b35be609 tests: signorm fix 2026-05-22 21:20:32 +02:00
Emil J. Tywoniak 72b60b6cef signorm: safer indexing if broken invariant 2026-05-22 18:41:50 +02:00
Emil J. Tywoniak dcc68e49fb check: check bufnorm too 2026-05-22 18:41:50 +02:00
Emil J. Tywoniak 4bff2e6340 check: check signorm indices and wires 2026-05-22 18:41:49 +02:00
Emil J. Tywoniak b9eae3f64b rtlil: publish signorm fanout 2026-05-22 18:41:49 +02:00
Emil J. Tywoniak 8f62d5c657 opt_merge: newcelltypes 2026-05-22 18:41:49 +02:00
Emil J. Tywoniak 7d335ed0d9 opt_merge: factor out hashing code across incremental and parallel 2026-05-22 18:41:49 +02:00
Emil J. Tywoniak 9abee44602 opt_expr: replace invert_map with signorm traversal 2026-05-22 18:41:49 +02:00
Emil J. Tywoniak 5dce475325 signorm: add timers 2026-05-22 18:40:16 +02:00
Emil J. Tywoniak 5de8452b57 rtlil_bufnorm: fix setup_driven_wires constant handling on unknown port direction 2026-05-22 18:40:16 +02:00