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yosys
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18230 Commits

Author SHA1 Message Date
Akash Levy b2b1e651f7 Fix macOS wheel: use Python 3.13 via setup-python, switch to macos-15 
The macos-14 runner ships Python 3.14 by default, producing wheels
incompatible with Python 3.13 environments. Pin to 3.13 using
actions/setup-python and switch to macos-15 for consistency.

Made-with: Cursor
 2026-02-28 19:33:39 -08:00
Akash Levy fe8d302472 fix: add retries to macOS wheel upload for race condition with Linux job 
Made-with: Cursor
 2026-02-28 18:53:38 -08:00
Akash Levy 1bb440ef15 refactor: build wheels only (no tarballs) for linux amd64 and macOS arm64 
Remove standalone tarball builds. The release now produces only
pyosys Python wheels for both platforms.

Made-with: Cursor
 2026-02-28 18:14:48 -08:00
Akash Levy 3d5cb87c90 Fix macOS build: remove pip3 install pybind11 
pybind11 is not needed since ENABLE_PYOSYS=0, and pip3 fails on
the macos-15 runner due to externally-managed-environment.

Made-with: Cursor
 2026-02-28 18:02:51 -08:00
Akash Levy e2b343a34f Fix macOS build: install ccache, disable pyosys 
The macOS runner doesn't have ccache or pybind11 pre-installed.
Install ccache via brew and disable ENABLE_PYOSYS since we only
need the binary tarball (not the wheel) for macOS.

Made-with: Cursor
 2026-02-28 17:27:20 -08:00
Akash Levy 9e29b7d761 Add macOS arm64 build to release workflow 
Adds a build-macos job on macos-15 that builds Verific tclmain and
yosys with SMALL=1, bundles non-system dylibs, and uploads
yosys-macos-arm64.tar.gz alongside the existing Linux assets.

Made-with: Cursor
 2026-02-28 16:49:32 -08:00
Akash Levy df261f46e3 feat: bundle shared library deps and set RPATH in release tarball 
Copies all non-system shared library dependencies into lib/, then
uses patchelf to set RPATH to $ORIGIN/../lib for bin/ executables
and $ORIGIN for lib/ libraries.

Made-with: Cursor
 2026-02-28 15:26:53 -08:00
Akash Levy 944d0b370a fix: clean between wheel and tarball builds to avoid TCL mismatch 
The wheel build uses ENABLE_TCL=0, but the standalone yosys binary
needs ENABLE_TCL=1. Without a clean, stale .o files cause undefined
reference errors for TCL symbols.

Made-with: Cursor
 2026-02-28 13:49:53 -08:00
Akash Levy fe4a997549 fix: add flex-dev for FlexLexer.h header 
Made-with: Cursor
 2026-02-28 13:14:04 -08:00
Akash Levy 402d6b0566 fix: add libdwarf-dev and elfutils-dev for backward-cpp headers 
Made-with: Cursor
 2026-02-28 12:38:16 -08:00
Akash Levy 7a35a982d3
Merge pull request #111 from Silimate/timing_balance_impl 
silimate: add opt_timing_balance pass and tests
 2026-02-28 12:22:23 -08:00
Akash Levy e7e15b6120 fix: add Alpine/musl shims for libtcl and libnsl 
Verific tclmain links -ltcl and -lnsl. Alpine tcl-dev provides
libtcl8.6.so (no libtcl.so symlink), and musl has no libnsl.
Create symlink and stub shared lib to satisfy the linker.

Made-with: Cursor
 2026-02-28 12:20:32 -08:00
Akash Levy 0b0c19b271 fix: use SSH_PRIVATE_KEY secret for private submodule access 
Use the same SSH key approach as source-vendor.yml for cloning
private submodules (abc, verific).

Made-with: Cursor
 2026-02-28 12:09:28 -08:00
Akash Levy 708637f65a fix: use PAT for private submodule access (abc, verific) 
Deploy keys are repo-scoped and can't access multiple private repos.
Use a PAT (SUBMODULE_PAT) that has access to all required repos.

Made-with: Cursor
 2026-02-28 12:07:03 -08:00
Akash Levy 44beeb5213 fix: use SSH deploy key for private verific submodule checkout 
Made-with: Cursor
 2026-02-28 12:05:26 -08:00
Akash Levy 2c1d160930 fix: trigger release workflow on main branch, not master 
Made-with: Cursor
 2026-02-28 12:03:52 -08:00
AdvaySingh1 877e97de06 Changed to for chacterization 2026-02-27 15:23:50 -08:00
Akash Levy fc4ff6ecd2 Add release workflow 2026-02-27 15:01:06 -08:00
Akash Levy 18c3a0b907 Remove old linefile loops stuff 2026-02-27 14:53:44 -08:00
Advay Singh 8974f3473f
Update passes/silimate/infer_ce.cc 
Co-authored-by: greptile-apps[bot] <165735046+greptile-apps[bot]@users.noreply.github.com>
 2026-02-27 12:37:49 -08:00
AdvaySingh1 90aa1cc016 Checked out main passes/techmap/clockgate.cc for source attributes and removed logging 2026-02-27 12:24:31 -08:00
AdvaySingh1 ce95d7cbcf Removed notes.txt 2026-02-27 12:22:29 -08:00
Stan Lee 8ee71ddc7f bugfix 2026-02-27 12:19:14 -08:00
Stan Lee 93af5a5232 in order 2026-02-27 12:17:43 -08:00
Stan Lee c42d2c2d03 support for nested structs 2026-02-27 11:54:43 -08:00
Stan Lee d36e2f7d17 resolve accidental change 2026-02-27 11:40:13 -08:00
Stan Lee 03ce300b49 another indent 2026-02-27 11:29:31 -08:00
Stan Lee fa1267e0cb fix indents 2026-02-27 11:27:37 -08:00
Stan Lee ae3b9b74e2 ready 2026-02-27 11:25:10 -08:00
Stan Lee 48894488f1 better method for assigning fsthandles 2026-02-27 11:25:10 -08:00
Stan Lee 0aaca679ce better but not ideal 2026-02-27 11:25:10 -08:00
Stan Lee 5bdc2d3451 working implementation that i will improvee further 2026-02-27 11:25:10 -08:00
AdvaySingh1 3cee420bf9 Merge branch 'main' into sat_clkgate 2026-02-27 11:15:22 -08:00
tondapusili f46b8d2a44 silimate: add opt_timing_balance pass and tests 2026-02-27 09:13:39 -08:00
Akash Levy 0c663bef4a
Merge pull request #110 from Silimate/negopt_log_flush 
Added log flushes after each negopt pass for clearer logging
 2026-02-26 16:09:34 -08:00
Stan Lee 29a1c69f74 move log flush to better spot 2026-02-26 16:01:37 -08:00
Stan Lee b11eef4fe1 fix bug 2026-02-26 16:00:27 -08:00
tondapusili 2f276d0723 Added log flushes after each negopt pass for clearer logging 2026-02-25 12:15:46 -08:00
Akash Levy 0b46d8b201
Merge pull request #109 from Silimate/clkgate_attr 
Added is_clock_gated attr to flops created via clockgate.cc pass
 2026-02-20 17:02:02 -08:00
Akash Levy c47dd20140
Merge pull request #108 from Silimate/icg_builtin_sim 
Added built in  cell alongside sim support for cell
 2026-02-20 17:01:20 -08:00
AdvaySingh1 ec537b189f Added is_clock_gated attr to flops created via clockgate.cc pass 2026-02-20 11:34:50 -08:00
AdvaySingh1 8f5b8cb46c Added is_clock_gated attr to flops created via clockgate.cc pass 2026-02-20 11:34:08 -08:00
AdvaySingh1 84a03a6b9a Merge branch 'icg_builtin_sim' into sat_clkgate 2026-02-19 11:51:49 -08:00
AdvaySingh1 b29514fafc Added built in cell alongside sim support for cell 2026-02-19 11:48:35 -08:00
AdvaySingh1 d9867fc7c7 Merge branch 'main' into sat_clkgate 2026-02-19 09:43:22 -08:00
AdvaySingh1 5e58bf22e0 Changed param naming for consistancy 2026-02-19 09:42:59 -08:00
Akash Levy 723ddd74cf Improve wreduce runtime 2026-02-19 01:03:26 -08:00
Akash Levy bf4ce9d6f7 Import uniquify fix 2026-02-19 00:24:32 -08:00
Akash Levy 3e9a5c68b1 Switch back to main Verific without VHDL support 2026-02-18 21:57:14 -08:00
Akash Levy 9a30512cff
Merge pull request #107 from Silimate/clkgate_node_retention 
Added node retention
 2026-02-18 18:17:27 -08:00