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18230 Commits

Author SHA1 Message Date
Maxim Kudinov 5b94a97fb3 gowin: synth_gowin: Add -nodsp option 2026-02-12 13:58:47 +03:00
Maxim Kudinov 542b29fa6a gowin: synth_gowin: Merge flatten label with coarse 2026-02-12 13:58:47 +03:00
Maxim Kudinov 5ea073d45e gowin: format MULT instances 2026-02-12 13:35:49 +03:00
Miodrag Milanović 9b9e7b5ae3
Merge pull request #3389 from uwsampl/support-parameter-default-values-in-json-frontend-and-verilog-backend 
Support parameter default values in JSON frontend and Verilog backend
 2026-02-12 10:17:56 +01:00
Miodrag Milanović ce5321da8c
Merge pull request #5682 from YosysHQ/update_abc 
Update ABC as per 2026-02-11
 2026-02-12 08:05:23 +01:00
AdvaySingh1 481e49954d Added notes for a fixed input_set_is_enable implementation 2026-02-11 17:05:13 -08:00
github-actions[bot] 1319112913 Bump version 2026-02-12 00:32:36 +00:00
AdvaySingh1 532d1d45a8 Resolved adding SigBits from Q using static EXCLUDE_Q_FROM_ENABLE knob 2026-02-11 15:08:49 -08:00
AdvaySingh1 4ca4392e9b Simplied recursion in sat_clockgate pass 2026-02-11 14:56:46 -08:00
AdvaySingh1 19060eeee7 Added TODO for how to add the COI set 2026-02-11 14:40:32 -08:00
AdvaySingh1 143a860673 Added future TODOs 2026-02-11 14:39:47 -08:00
AdvaySingh1 da8febc3b7 Added to notes.txt 2026-02-11 14:22:26 -08:00
AdvaySingh1 d2300b2a9f Added nodes for the MITER 2026-02-11 14:19:29 -08:00
AdvaySingh1 dd3f2e370c Fixed naming for bfs_find_potential_enable_inputs 2026-02-11 12:31:13 -08:00
AdvaySingh1 5b384511f2 Added initial SatClockgateWorker 2026-02-11 11:02:15 -08:00
AdvaySingh1 9e544aa95c Added pseudocode for create_ce_logic 2026-02-11 11:01:49 -08:00
AdvaySingh1 b4cd82bacf Added initial printing of the clocks with dump_flipflops_to_file 2026-02-11 10:56:07 -08:00
AdvaySingh1 5aeb19fb66 Added initial version 1 pseudocode 2026-02-11 10:55:43 -08:00
AdvaySingh1 e4f69cba30 Initialized notes 2026-02-11 09:53:03 -08:00
Gus Smith 7a0774c3bb Don't dump params by default 2026-02-11 08:33:39 -08:00
Emil J b890b1b43f
Merge pull request #5678 from YosysHQ/emil/remove-dockerfile 
Dockerfile: remove
 2026-02-11 17:32:21 +01:00
Miodrag Milanovic a13b5c4211 Update ABC as per 2026-02-11 2026-02-11 17:30:08 +01:00
Gus Smith be9c857e72 Fix ABC after merge 2026-02-11 08:12:38 -08:00
Gus Smith b0021e5b10 Add tests 2026-02-11 08:10:57 -08:00
Gus Smith 1ede98797f Update backends/verilog/verilog_backend.cc 
Co-authored-by: Marcelina Kościelnicka <236399+mwkmwkmwk@users.noreply.github.com>
 2026-02-11 08:10:57 -08:00
Gus Smith 9ad7aed4a5 Update backends/verilog/verilog_backend.cc 
Co-authored-by: Marcelina Kościelnicka <236399+mwkmwkmwk@users.noreply.github.com>
 2026-02-11 08:10:57 -08:00
Gus Smith 12ace45b89 Support param. default values in JSON FE and SV BE 2026-02-11 08:10:55 -08:00
Gus Smith e3db8fee6f
Merge pull request #3459 from gs-jgj/feature_dsp48e1_presub 
Add support for subtract in preadder
 2026-02-11 08:02:18 -08:00
Gus Smith 8ab105ac28
Merge pull request #4303 from Coloquinte/sat_choice 
Infrastructure to run a Sat solver as a command
 2026-02-11 06:54:53 -08:00
Emil J fba29ea8f1
Merge pull request #5679 from YosysHQ/emil/abc9-remove-liberty 
abc9: remove -liberty
 2026-02-11 12:36:29 +01:00
Emil J. Tywoniak 3f1fbfdaee blifparse: add bounds check 2026-02-11 12:16:02 +01:00
Emil J. Tywoniak 915912cc76 abc9: remove -dont_use 2026-02-11 11:39:09 +01:00
Emil J. Tywoniak c4094e457b abc9: remove -genlib, -constr 2026-02-11 11:34:54 +01:00
Emil J. Tywoniak fe613f29b9 .github: move gtest to build dependencies 2026-02-11 11:33:27 +01:00
Emil J. Tywoniak 5a46106a46 abc9: remove -liberty 2026-02-11 01:04:50 +01:00
Emil J. Tywoniak a6a07fb39c Dockerfile: remove 2026-02-11 00:59:12 +01:00
Emil J. Tywoniak 98c3f03497 docs: clarify vanilla test run-test.sh 2026-02-11 00:58:29 +01:00
Emil J. Tywoniak dfbef2fe24 .github: run unit tests in build jobs, not test jobs 2026-02-11 00:55:36 +01:00
AdvaySingh1 6ad01fa850 Added initial pass structure 2026-02-10 14:33:37 -08:00
AdvaySingh1 b53acb0ff0 Added pass in Makefile.inc 2026-02-10 14:33:17 -08:00
AdvaySingh1 b4ef420c3f Added inital SAT based clock gating file 2026-02-10 14:02:15 -08:00
Krystine Sherwin 9f30f0e7d6
test-build: Don't rebuild OBJS 2026-02-10 15:34:47 +13:00
Krystine Sherwin 030e495c8b
test-build: Build and cache libyosys.so 2026-02-10 15:05:17 +13:00
github-actions[bot] a6e33d9916 Bump version 2026-02-10 00:38:43 +00:00
Emil J d2f7d3cf63
Merge pull request #5665 from rocallahan/abc-tmp-path 
Sanitize ABC global and per-run temporary directory names in logs
 2026-02-09 23:26:57 +01:00
Emil J. Tywoniak ff9cd0eed7 Makefile: test target requires unit-test, add vanilla-test for old test target 2026-02-09 23:21:24 +01:00
Gus Smith b04948a8cd Simplify test 2026-02-09 09:38:45 -08:00
Gus Smith 6f6fa49d3c Typo 2026-02-09 09:05:56 -08:00
Rowan Goemans b8ee50d77f kernel/celledges: cover more cell types 2026-02-09 14:13:40 +01:00
Akash Levy f8a095e404
Merge pull request #105 from Silimate/negopt-fixes 
fixed edge cases in negopt passes, fixed cell naming inconsistencies
 2026-02-08 23:37:04 -08:00