add -pg also in LDFLAGS if --profile is requested; add little more margin in ps page exports
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63f266c905
commit
d64c8abb40
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@ -221,11 +221,16 @@ int hook_detect_target()
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if (require("cc/argstd/pg", 0, 0) == 0) {
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append("cc/cflags", " ");
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append("cc/cflags", get("cc/argstd/pg"));
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append("cc/ldflags", " ");
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append("cc/ldflags", get("cc/argstd/pg"));
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}
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/* no-pie no more needed it seems */
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/*
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if (require("cc/argstd/no-pie", 0, 0) == 0) {
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append("cc/cflags", " ");
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append("cc/cflags", get("cc/argstd/no-pie"));
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}
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*/
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}
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}
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@ -1064,7 +1064,6 @@ void propagate_logic()
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npin = xctx->simdata.inst[i].npin;
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for(j=0; j<npin;j++) {
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if(xctx->simdata.inst && xctx->simdata.inst[i].pin && xctx->simdata.inst[i].pin[j].go_to) {
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/* if(xctx->simdata.inst[i].pin[j].go_to) { */
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int n = 1;
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const char *propag;
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int clock_pin, clock_val, clock_oldval;
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@ -577,7 +577,7 @@ void ps_draw(void)
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{
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double dx, dy, scale, scaley;
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int landscape=1;
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double margin=0; /* in postscript points, (1/72)". No need to add margin as xschem zoom full already has margins.*/
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double margin=10; /* in postscript points, (1/72)". No need to add margin as xschem zoom full already has margins.*/
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/* Legal: 612 792 */
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double pagex=842;/* a4, in postscript points, (1/72)" */
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@ -1,5 +1,6 @@
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v {xschem version=2.9.5 file_version=1.1}
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v {xschem version=2.9.9 file_version=1.2 }
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G {}
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K {}
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V {}
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S {}
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E {}
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@ -10,7 +11,7 @@ Distributed under the terms of the GNU General Public License,
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either verion 2 or (at your choice) any later version.} 40 -150 0 0 0.4 0.4 {}
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T {INPUTS} 50 -520 0 0 0.4 0.4 {}
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T {OUTPUTS} 280 -460 0 0 0.4 0.4 {}
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T {Binary to 7-segment chip} 660 -450 0 0 0.7 0.7 {}
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T {Binary to 7-segment chip} 660 -460 0 0 0.7 0.7 {}
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N 500 -610 590 -610 {lab=bcd2[1:0]}
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N 590 -630 590 -610 {lab=bcd2[1:0]}
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N 590 -630 650 -630 {lab=bcd2[1:0]}
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@ -109,7 +110,7 @@ C {ipin.sym} 110 -480 0 0 {name=p15 lab=ibin[7:0]}
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C {opin.sym} 280 -420 0 0 {name=p6 lab=oseg2[6:0] verilog_type=reg}
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C {opin.sym} 280 -400 0 0 {name=p7 lab=oseg1[6:0] verilog_type=reg}
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C {opin.sym} 280 -380 0 0 {name=p8 lab=oseg0[6:0] verilog_type=reg}
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C {code.sym} 700 -170 0 0 {name=TESTBENCH only_toplevel=false value="
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C {code.sym} 790 -160 0 0 {name=TESTBENCH only_toplevel=false value="
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reg [7:0] iibin;
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reg ien;
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reg inen;
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@ -119,7 +120,7 @@ reg ipolarity;
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initial begin
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$dumpfile(\\"dumpfile.vcd\\");
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$dumpvars;
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$dumpvars(0, top);
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end
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task binpattern;
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@ -1,4 +1,4 @@
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v {xschem version=2.9.8 file_version=1.2}
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v {xschem version=2.9.9 file_version=1.2 }
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G {}
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K {type=resistor
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format="@name @pinlist @value m=@m"
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@ -36,10 +36,10 @@ L 4 2.5 -22.5 7.5 -22.5 {}
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L 4 5 -25 5 -20 {}
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B 5 -2.5 -32.5 2.5 -27.5 {name=P dir=inout propag=1 pinnumber=1}
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B 5 -2.5 27.5 2.5 32.5 {name=M dir=inout propag=0 pinnumber=2}
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T {@name} 15 -18.75 0 0 0.2 0.2 {}
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T {@name} -15 -13.75 0 1 0.2 0.2 {}
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T {@value} 15 -6.25 0 0 0.2 0.2 {}
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T {@#0:pinnumber} -10 -26.25 0 1 0.2 0.2 {layer=13}
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T {@#1:pinnumber} -10 16.25 0 1 0.2 0.2 {layer=13}
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T {@#0:net_name} 10 -28.75 0 0 0.15 0.15 {layer=15}
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T {@#1:net_name} 10 20 0 0 0.15 0.15 {layer=15}
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T {m=@m} 15 6.25 0 0 0.2 0.2 {}
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T {m=@m} -15 1.25 0 1 0.2 0.2 {}
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