removed unused files

This commit is contained in:
Stefan Schippers 2020-08-24 10:01:41 +02:00
parent 9070aaeb07
commit bd982c00ce
49 changed files with 0 additions and 4625 deletions

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@ -1,34 +0,0 @@
if you are to use this as presentation, live, I recommend making the 'next' link bigger - like the whole bottom line or even the whole background should be link to the next page
on slide 5 I find the headers strange
especially 'item'
GUI toolkit: TCL; are you sure it's not called TCL/Tk?
stefan
ok, well, this was done the lazy way by grabbing a table image , willl rewrite with HTML table.
Igor2
(as far as I understood tcl doesn't do GUI)
stefan
thanks will correct
stefan
the table was a side-by side comparison of xschem vs Cadence Virtuoso, of course i removed the Cadence column :-)
willl redo this slide
slide9: I'd remove the download link from here, and would add a 'thank you and good bye' slide as slide 10 with the home page URL, svn URL and contact (at least email)
a list of all the different simulators you support, maybe with a short comment on how well that flow works, pros, cons
- a slide about how you create a symbol (steps) just to show it's not different and not complicated
another important point, especially after seeing so much fosdem:
some listeners will find your presentation inspirative and will write a mail soon after the presentation
but if you do a demo, I'd skip these, these are less interesting than the demo
another important point, especially after seeing so much fosdem:
some listeners will find your presentation inspirative and will write a mail soon after the presentation
make sure you allocate some time and access your mail within some reasonable time frame (like 6 or 12 hours) after the presentation
it's rather disappointing when the presenter answers only after week
"because I had to get home first", "but if I was there I decided to spend 2 days", etc
being able to react in reasonable time shows the listeners are really important to you, not only the show

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@ -1,163 +0,0 @@
### PLEASE DO NOT EDIT THIS FILE, it has been generated from Makefile.in. ###
TESTER=../tester
all: Tutor01_hello.diff Tutor02_vars.diff Tutor03_blocks.diff Tutor04_if.diff Tutor05_switch.diff Tutor06_foreach.diff Tutor07_sub.diff Tutor08_uniq.diff Tutor09_ui.diff Tutor10_include_redir.diff Tutor11_missing.diff Tutor12_halt.diff comment.diff foreach.diff if.diff switch.diff test.diff then.diff append.diff order.diff err_if_end.diff err_if_else.diff err_excess_end.diff err_switch_end.diff err_switch_nocond.diff err_no_end.diff
# Explicit test rules
Tutor01_hello.out: Tutor01_hello.gasm $(TESTER) Makefile
$(TESTER) < Tutor01_hello.gasm > Tutor01_hello.out 2>&1
Tutor01_hello.diff: Tutor01_hello.ref Tutor01_hello.out
diff -u Tutor01_hello.ref Tutor01_hello.out
Tutor02_vars.out: Tutor02_vars.gasm $(TESTER) Makefile
$(TESTER) < Tutor02_vars.gasm > Tutor02_vars.out 2>&1
Tutor02_vars.diff: Tutor02_vars.ref Tutor02_vars.out
diff -u Tutor02_vars.ref Tutor02_vars.out
Tutor03_blocks.out: Tutor03_blocks.gasm $(TESTER) Makefile
$(TESTER) < Tutor03_blocks.gasm > Tutor03_blocks.out 2>&1
Tutor03_blocks.diff: Tutor03_blocks.ref Tutor03_blocks.out
diff -u Tutor03_blocks.ref Tutor03_blocks.out
Tutor04_if.out: Tutor04_if.gasm $(TESTER) Makefile
$(TESTER) < Tutor04_if.gasm > Tutor04_if.out 2>&1
Tutor04_if.diff: Tutor04_if.ref Tutor04_if.out
diff -u Tutor04_if.ref Tutor04_if.out
Tutor05_switch.out: Tutor05_switch.gasm $(TESTER) Makefile
$(TESTER) < Tutor05_switch.gasm > Tutor05_switch.out 2>&1
Tutor05_switch.diff: Tutor05_switch.ref Tutor05_switch.out
diff -u Tutor05_switch.ref Tutor05_switch.out
Tutor06_foreach.out: Tutor06_foreach.gasm $(TESTER) Makefile
$(TESTER) < Tutor06_foreach.gasm > Tutor06_foreach.out 2>&1
Tutor06_foreach.diff: Tutor06_foreach.ref Tutor06_foreach.out
diff -u Tutor06_foreach.ref Tutor06_foreach.out
Tutor07_sub.out: Tutor07_sub.gasm $(TESTER) Makefile
$(TESTER) < Tutor07_sub.gasm > Tutor07_sub.out 2>&1
Tutor07_sub.diff: Tutor07_sub.ref Tutor07_sub.out
diff -u Tutor07_sub.ref Tutor07_sub.out
Tutor08_uniq.out: Tutor08_uniq.gasm $(TESTER) Makefile
$(TESTER) < Tutor08_uniq.gasm > Tutor08_uniq.out 2>&1
Tutor08_uniq.diff: Tutor08_uniq.ref Tutor08_uniq.out
diff -u Tutor08_uniq.ref Tutor08_uniq.out
Tutor09_ui.out: Tutor09_ui.gasm $(TESTER) Makefile
$(TESTER) < Tutor09_ui.gasm > Tutor09_ui.out 2>&1
Tutor09_ui.diff: Tutor09_ui.ref Tutor09_ui.out
diff -u Tutor09_ui.ref Tutor09_ui.out
Tutor10_include_redir.out: Tutor10_include_redir.gasm $(TESTER) Makefile
$(TESTER) < Tutor10_include_redir.gasm > Tutor10_include_redir.out 2>&1
Tutor10_include_redir.diff: Tutor10_include_redir.ref Tutor10_include_redir.out
diff -u Tutor10_include_redir.ref Tutor10_include_redir.out
Tutor11_missing.out: Tutor11_missing.gasm $(TESTER) Makefile
$(TESTER) < Tutor11_missing.gasm > Tutor11_missing.out 2>&1
Tutor11_missing.diff: Tutor11_missing.ref Tutor11_missing.out
diff -u Tutor11_missing.ref Tutor11_missing.out
Tutor12_halt.out: Tutor12_halt.gasm $(TESTER) Makefile
$(TESTER) < Tutor12_halt.gasm > Tutor12_halt.out 2>&1
Tutor12_halt.diff: Tutor12_halt.ref Tutor12_halt.out
diff -u Tutor12_halt.ref Tutor12_halt.out
comment.out: comment.gasm $(TESTER) Makefile
$(TESTER) < comment.gasm > comment.out 2>&1
comment.diff: comment.ref comment.out
diff -u comment.ref comment.out
foreach.out: foreach.gasm $(TESTER) Makefile
$(TESTER) < foreach.gasm > foreach.out 2>&1
foreach.diff: foreach.ref foreach.out
diff -u foreach.ref foreach.out
if.out: if.gasm $(TESTER) Makefile
$(TESTER) < if.gasm > if.out 2>&1
if.diff: if.ref if.out
diff -u if.ref if.out
switch.out: switch.gasm $(TESTER) Makefile
$(TESTER) < switch.gasm > switch.out 2>&1
switch.diff: switch.ref switch.out
diff -u switch.ref switch.out
test.out: test.gasm $(TESTER) Makefile
$(TESTER) < test.gasm > test.out 2>&1
test.diff: test.ref test.out
diff -u test.ref test.out
then.out: then.gasm $(TESTER) Makefile
$(TESTER) < then.gasm > then.out 2>&1
then.diff: then.ref then.out
diff -u then.ref then.out
append.out: append.gasm $(TESTER) Makefile
$(TESTER) < append.gasm > append.out 2>&1
append.diff: append.ref append.out
diff -u append.ref append.out
order.out: order.gasm $(TESTER) Makefile
$(TESTER) < order.gasm > order.out 2>&1
order.diff: order.ref order.out
diff -u order.ref order.out
err_if_end.out: err_if_end.gasm $(TESTER) Makefile
$(TESTER) < err_if_end.gasm > err_if_end.out 2>&1
err_if_end.diff: err_if_end.ref err_if_end.out
diff -u err_if_end.ref err_if_end.out
err_if_else.out: err_if_else.gasm $(TESTER) Makefile
$(TESTER) < err_if_else.gasm > err_if_else.out 2>&1
err_if_else.diff: err_if_else.ref err_if_else.out
diff -u err_if_else.ref err_if_else.out
err_excess_end.out: err_excess_end.gasm $(TESTER) Makefile
$(TESTER) < err_excess_end.gasm > err_excess_end.out 2>&1
err_excess_end.diff: err_excess_end.ref err_excess_end.out
diff -u err_excess_end.ref err_excess_end.out
err_switch_end.out: err_switch_end.gasm $(TESTER) Makefile
$(TESTER) < err_switch_end.gasm > err_switch_end.out 2>&1
err_switch_end.diff: err_switch_end.ref err_switch_end.out
diff -u err_switch_end.ref err_switch_end.out
err_switch_nocond.out: err_switch_nocond.gasm $(TESTER) Makefile
$(TESTER) < err_switch_nocond.gasm > err_switch_nocond.out 2>&1
err_switch_nocond.diff: err_switch_nocond.ref err_switch_nocond.out
diff -u err_switch_nocond.ref err_switch_nocond.out
err_no_end.out: err_no_end.gasm $(TESTER) Makefile
$(TESTER) < err_no_end.gasm > err_no_end.out 2>&1
err_no_end.diff: err_no_end.ref err_no_end.out
diff -u err_no_end.ref err_no_end.out

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@ -1,16 +0,0 @@
print [at 7:1]
arg: {hello world!
}
print [at 11:1]
arg: {hello}
arg: {world!}
arg: {
}
print [at 14:1]
print [at 17:1]
arg: {HELLO}
print [at 17:16]
arg: { WORLD!}
print [at 17:36]
arg: {
}

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@ -1,36 +0,0 @@
put [at 4:1]
arg: myvar
arg: {Hello world!
}
print [at 7:1]
arg: myvar
print [at 11:1]
arg: {Hello universe! }
arg: myvar
put [at 15:1]
arg: str
arg: {cats raining from the sky}
put [at 16:1]
arg: tmp
arg: str
print [at 17:1]
arg: str
arg: {==}
arg: tmp
arg: {
}
print [at 21:1]
arg: {safe get: '}
arg: ?nonexist
arg: {'
}
print [at 25:1]
arg: {exists (no): }
arg: &nonexist
arg: {
}
print [at 26:1]
arg: {exists (yes): }
arg: &myvar
arg: {
}

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@ -1,35 +0,0 @@
print [at 7:1]
arg: {this is a string}
arg: {
}
print [at 9:1]
arg: {--
}
put [at 11:1]
arg: myblk
arg: {a block
of multiline
data.
}
print [at 16:1]
arg: myblk
put [at 24:1]
arg: myvar
arg: {world}
print [at 25:1]
arg: {--
}
print [at 26:1]
arg: [~ hello ~myvar~! ~]
arg: {
}
print [at 27:1]
arg: {--
}
print [at 28:1]
arg: {
hi @myvar@!
}
print [at 31:1]
arg: {--
}

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@ -1,42 +0,0 @@
put [at 1:1]
arg: myvar
arg: {true}
if myvar [at 6:10]
then:
print [at 7:2]
arg: {myvar is true (1)
}
else:
print [at 9:2]
arg: {myvar is false (1)
}
if myvar [at 14:10]
then:
print [at 15:2]
arg: {myvar is true (2)
}
else:
(NOP)
if myvar [at 19:10]
then:
(NOP)
else:
print [at 20:2]
arg: {myvar is false (3)
}
put [at 24:1]
arg: foo
arg: {false}
if myvar [at 25:10]
then:
if foo [at 26:9]
then:
print [at 27:3]
arg: {myvar and bar are true (4)
}
else:
print [at 29:3]
arg: {myvar is true, bar is false (4)
}
else:
(NOP)

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@ -1,71 +0,0 @@
put [at 15:1]
arg: myvar
arg: {foobar}
switch myvar [at 16:1]
case {baz}
put [at 17:14]
arg: res
arg: {1}
print [at 17:27]
arg: {this is baz.
}
case {^oob}
put [at 18:14]
arg: res
arg: {2}
print [at 18:27]
arg: {did you mean out-of-band?
}
case {^f}
put [at 19:14]
arg: res
arg: {3}
print [at 19:27]
arg: {starts with f.
}
case {oob}
put [at 20:14]
arg: res
arg: {4}
print [at 20:27]
arg: {OOB!
}
default
put [at 21:14]
arg: res
arg: {0}
print [at 21:27]
arg: {none.
}
print [at 24:1]
arg: {result is: }
arg: res
arg: {
}
put [at 28:1]
arg: patt
arg: {^number$}
put [at 29:1]
arg: REF
arg: {3}
switch [~num ~res~ ber~] [at 30:1]
case patt
print [at 31:23]
arg: {empty
}
case [~^num ~REF~~]
print [at 32:23]
arg: {reference
}
put [at 38:1]
arg: cond
arg: {blobb}
switch cond [at 39:1]
case {lob}
print [at 40:15]
arg: {"then"
}
default
print [at 41:15]
arg: {"else"
}

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@ -1,32 +0,0 @@
foreach item in {this is a list of words} [at 7:1]
print [at 8:2]
arg: item
arg: {
}
put [at 15:1]
arg: nl
arg: {
}
foreach item in {foo bar baz} [at 16:1]
foreach w in [~next: ~item~~nl~~] [at 17:2]
print [at 18:3]
arg: w
put [at 27:1]
arg: libs
arg: {-lsdl -ltcl8.4}
foreach l in libs [at 28:1]
print [at 29:2]
arg: {l=}
arg: l
arg: {
}
switch l [at 30:2]
case {^-lsdl}
put [at 31:19]
arg: libs
arg: [~-lm ~libs~ -lsvga~]
print [at 34:1]
arg: {libs=}
arg: libs
arg: {
}

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@ -1,40 +0,0 @@
put [at 6:1]
arg: myvar
arg: {Hello world!
}
sub [at 7:1]
arg: myvar
arg: {l}
arg: {2}
print [at 8:1]
arg: myvar
sub [at 13:1]
arg: {myvar}
arg: {l}
arg: {3}
print [at 14:1]
arg: myvar
put [at 19:1]
arg: pointer
arg: {myvar}
sub [at 20:1]
arg: [~~pointer~~]
arg: {l}
arg: {4}
print [at 21:1]
arg: myvar
put [at 25:1]
arg: punctuation
arg: {[!?.]}
sub [at 26:1]
arg: [~~pointer~~]
arg: punctuation
arg: [~ PUNCT:~punctuation~~]
print [at 27:1]
arg: myvar
gsub [at 30:1]
arg: [~~pointer~~]
arg: {o}
arg: {_0_}
print [at 31:1]
arg: myvar

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@ -1,89 +0,0 @@
put [at 7:1]
arg: list
arg: {this
is
a
list
of
words,
a
list
of
words.
}
print [at 18:1]
arg: {original:
}
arg: list
arg: {
}
uniq [at 19:1]
arg: list
print [at 20:1]
arg: {uniq:
}
arg: list
arg: {
}
put [at 24:1]
arg: foo
arg: {this
foo
is
a
this
foo
}
uniq [at 31:1]
arg: tmp
arg: foo
print [at 32:1]
arg: {original:
}
arg: foo
arg: {
uniq:
}
arg: tmp
arg: {
}
sortuniq [at 39:1]
arg: tmp
arg: foo
print [at 40:1]
arg: {
sortuniq:
}
arg: tmp
arg: {
}
put [at 49:1]
arg: list
arg: {#define foo
#include "foo20.h"
#include "foo10.h"
/* misc1 */
#define bar
#include "bar1.h"
#include "bar2.h"
/* misc2 */
}
put [at 61:1]
arg: /tmpasm/IFS
arg: {
}
uniq [at 63:1]
arg: tmp
arg: list
arg: {^#define}
arg: {^#include}
print [at 64:1]
arg: {original:
}
arg: list
arg: {
grouped uniq:
}
arg: tmp
arg: {
}

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@ -1,11 +0,0 @@
put [at 9:1]
arg: myvar
arg: {!
}
report [at 10:1]
arg: {hello }
arg: {world}
arg: myvar
report [at 11:1]
arg: [~hello world~myvar~~]
abort [at 15:1]

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@ -1,20 +0,0 @@
print [at 14:1]
arg: {this goes to the default output
}
redir [at 18:1]
arg: {Tutor10.inc}
print [at 19:1]
arg: {# this is a generated file.}
print [at 20:1]
arg: {
print {hello world from my include!\n}
}
redir [at 25:1]
print [at 26:1]
arg: {back at default output.
}
print [at 45:1]
arg: {Include:
}
include [at 46:1]
arg: {Tutor10.inc}

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@ -1,17 +0,0 @@
put [at 6:1]
arg: tmp
arg: {true}
if tmp [at 7:8]
then:
foreach item in {foo bar true baz} [at 8:2]
print [at 9:3]
arg: item
arg: {
}
if item [at 10:11]
then:
halt [at 11:4]
else:
(NOP)
else:
(NOP)

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@ -1,15 +0,0 @@
append [at 1:1]
arg: tmp
arg: {foo}
append [at 2:1]
arg: tmp
arg: {bar}
append [at 3:1]
arg: tmp
arg: {baz}
foreach n in tmp [at 4:1]
print [at 5:2]
arg: {-> }
arg: n
arg: {
}

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@ -1,4 +0,0 @@
print [at 1:1]
arg: data1
print [at 2:1]
arg: data2

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@ -1,6 +0,0 @@
error: Excess "end" at 3:4
if {1} [at 1:8]
then:
(NOP)
else:
(NOP)

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@ -1,6 +0,0 @@
error: unexpected 'else' - must be in a 'then' block before an else at 2:5
if *NULL - broken AST* [at 1:1]
then:
(NOP)
else:
(NOP)

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@ -1,6 +0,0 @@
error: unexpected "end" in "if" - expected "then" at 2:4
if v [at 2:1]
then:
(NOP)
else:
(NOP)

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@ -1,6 +0,0 @@
pritn [at 1:1]
arg: {foo}
switch {cond} [at 2:1]
case {1}
print [at 3:11]
arg: {foo}

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@ -1,2 +0,0 @@
error: unexpected end of if switch statement; expected a data at 1:7
(NOP)

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@ -1,2 +0,0 @@
error: unexpected end of if switch statement; expected a data at 1:7
(NOP)

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@ -1,41 +0,0 @@
put [at 1:1]
arg: a
arg: {1}
put [at 2:1]
arg: foo
arg: {example-FOO}
put [at 3:1]
arg: bar
arg: {example-BAR}
put [at 4:1]
arg: baz
arg: {example-BAZ}
put [at 5:1]
arg: hah
arg: {haha}
foreach n in [~foo ~bar~ baz~] [at 9:1]
print [at 10:2]
arg: {n=}
arg: n
arg: {
}
print [at 11:2]
arg: {a11}
arg: [~a12 ~hah~ a14~]
arg: {
}
print [at 12:2]
arg: {a21}
arg: {a22 a23}
arg: {
}
print [at 13:2]
arg: {a31
}
print [at 15:1]
arg: {a41}
arg: {a42}
arg: {a43}
arg: {
}
print [at 16:1]

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@ -1,15 +0,0 @@
put [at 1:1]
arg: a
arg: 1
if a [at 2:6]
then:
if b [at 3:7]
then:
print [at 4:3]
arg: {then-then}
else:
print [at 6:3]
arg: {then-else}
else:
print [at 9:2]
arg: {else}

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@ -1,159 +0,0 @@
put [at 2:1]
arg: list
arg: {one two three four}
print [at 4:1]
arg: list
arg: {
}
print [at 6:1]
arg: {
nothing:
}
order [at 9:1]
arg: out
arg: list
arg: {one}
arg: {before}
arg: {two}
print [at 10:1]
arg: out
arg: {
}
order [at 12:1]
arg: out
arg: list
arg: {one}
arg: {before}
arg: {one}
print [at 13:1]
arg: out
arg: {
}
order [at 15:1]
arg: out
arg: list
arg: {one}
arg: {after}
arg: {one}
print [at 16:1]
arg: out
arg: {
}
order [at 18:1]
arg: out
arg: list
arg: {two}
arg: {after}
arg: {one}
print [at 19:1]
arg: out
arg: {
}
order [at 22:1]
arg: out
arg: list
arg: {nine}
arg: {after}
arg: {one}
print [at 23:1]
arg: out
arg: {
}
order [at 24:1]
arg: out
arg: list
arg: {one}
arg: {after}
arg: {nine}
print [at 25:1]
arg: out
arg: {
}
print [at 27:1]
arg: {
before:
}
order [at 28:1]
arg: out
arg: list
arg: {two}
arg: {before}
arg: {one}
print [at 29:1]
arg: out
arg: {
}
order [at 31:1]
arg: out
arg: list
arg: {four}
arg: {before}
arg: {one}
print [at 32:1]
arg: out
arg: {
}
order [at 34:1]
arg: out
arg: list
arg: {four}
arg: {before}
arg: {three}
print [at 35:1]
arg: out
arg: {
}
order [at 37:1]
arg: out
arg: list
arg: {three}
arg: {before}
arg: {two}
print [at 38:1]
arg: out
arg: {
}
print [at 40:1]
arg: {
after:
}
order [at 41:1]
arg: out
arg: list
arg: {one}
arg: {after}
arg: {two}
print [at 42:1]
arg: out
arg: {
}
order [at 44:1]
arg: out
arg: list
arg: {one}
arg: {after}
arg: {four}
print [at 45:1]
arg: out
arg: {
}
order [at 47:1]
arg: out
arg: list
arg: {two}
arg: {after}
arg: {three}
print [at 48:1]
arg: out
arg: {
}
order [at 50:1]
arg: out
arg: list
arg: {two}
arg: {after}
arg: {four}
print [at 51:1]
arg: out
arg: {
}

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@ -1,47 +0,0 @@
put [at 1:1]
arg: swdata
arg: {lol}
switch swdata [at 2:1]
case data1
print [at 3:24]
arg: {1a}
arg: {11}
print [at 3:41]
arg: {1b}
arg: 12
print [at 3:56]
arg: {1c}
arg: 13
print [at 3:71]
arg: {1d}
arg: 14
case [~data2 ~a~~]
print [at 4:24]
arg: {2a}
arg: 21
print [at 4:41]
arg: {2b}
arg: 22
print [at 4:56]
arg: {2c}
arg: 23
print [at 4:71]
arg: {2d}
arg: 24
default
print [at 5:24]
arg: {3a}
arg: 31
print [at 5:41]
arg: {3b}
arg: 32
print [at 5:56]
arg: {3c}
arg: 33
print [at 5:71]
arg: {3d}
arg: 34
print [at 7:1]
arg: {i1}
print [at 8:1]
arg: {i2}

View File

@ -1,62 +0,0 @@
put [at 2:1]
arg: /local/cflags
arg: {-std=c99 -Wall}
put [at 3:1]
arg: /local/ldflags
arg: {-lm}
put [at 4:1]
arg: /local/objs
arg: {main.o foo.o bar.o}
if /local/debug [at 7:17]
then:
append [at 8:2]
arg: /local/cflags
arg: {-g}
else:
append [at 10:2]
arg: /local/cflags
arg: {-O2}
isempty [at 14:1]
arg: /local/r
arg: /local/somelib
invert [at 15:1]
arg: /local/r
if /local/r [at 16:13]
then:
append [at 17:2]
arg: /local/cflags
arg: { -I/usr/include/somelib}
append [at 18:2]
arg: /local/ldflags
arg: { -lsomelib}
else:
(NOP)
print [at 22:1]
arg: [~
# Makefile generated by scconfig - DO NOT EDIT - please edit Makefile.in
CFLAGS=~/local/cflags~
LDFLAGS=~/local/ldflags~
OBJS=~/local/objs~
all: main
main: $(OBJS)
$(CC) $(LDFLAGS)
~]
foreach /local/o in /local/objs [at 38:1]
put [at 39:2]
arg: /local/c
arg: /local/o
sub [at 40:2]
arg: /local/c
arg: {.o$}
arg: {.c}
print [at 41:2]
arg: [~
~/local/o~: ~/local/c~
$(CC) -c $(CFLAGS) ~/local/c~ -o ~/local/o~
~]
print [at 47:1]
arg: {#end
}

View File

@ -1,12 +0,0 @@
if cnd [at 2:8]
then:
print [at 3:2]
arg: a1
arg: a2
arg: a3
else:
(NOP)
print [at 6:1]
arg: a1
arg: a2
arg: a3

Binary file not shown.

View File

@ -1,533 +0,0 @@
v {xschem version=2.9.7 file_version=1.2}
G {}
V {}
S {
}
E {}
L 4 250 -340 270 -360 {}
L 4 250 -340 290 -340 {}
L 4 270 -360 290 -340 {}
L 4 270 -260 290 -280 {}
L 4 250 -280 290 -280 {}
L 4 250 -280 270 -260 {}
L 4 270 -340 270 -280 {}
L 4 350 -620 370 -600 {}
L 4 370 -640 370 -600 {}
L 4 350 -620 370 -640 {}
L 4 370 -620 530 -620 {}
L 4 1400 -290 1420 -310 {}
L 4 1400 -330 1400 -290 {}
L 4 1400 -330 1420 -310 {}
L 4 1240 -310 1400 -310 {}
T {These 2 instances are equivalent} 290 -320 0 0 0.4 0.4 {}
T {Example of using a schematic as a
component instance instead of the
usual symbol.
LCC: Local Custom Cell.
LCC schematic instantiation show actual parameters
in the schematic instance.} 550 -840 0 0 0.6 0.6 {}
T {LCC schematics can be nested
If only .sch is used there is
no need for a .sym file at all} 910 -430 0 0 0.6 0.6 {}
N 410 -140 410 -120 {lab=HALF}
N 410 -230 430 -230 {lab=ZZ}
N 410 -230 410 -200 {lab=ZZ}
N 420 -440 420 -420 {lab=HALF}
N 420 -530 700 -530 {lab=Z}
N 420 -530 420 -500 {lab=Z}
N 700 -530 700 -240 {lab=Z}
N 700 -240 1450 -240 {lab=Z}
N 320 -230 410 -230 {lab=ZZ}
N 330 -530 420 -530 {lab=Z}
C {vsource.sym} 50 -140 0 0 {name=V1 value="pwl 0 0 1u 0 5u 3" embed=true}
[
v {xschem version=2.9.7 file_version=1.2}
G {type=vsource
format="@name @pinlist @value"
template="name=V1 value=3"}
V {}
S {}
E {}
L 4 2.5 -22.5 7.5 -22.5 {}
L 4 5 -25 5 -20 {}
L 4 -0 -30 -0 30 {}
B 5 -2.5 -32.5 2.5 -27.5 {name=p dir=inout}
B 5 -2.5 27.5 2.5 32.5 {name=m dir=inout}
A 4 0 0 15 270 360 {}
T {@value} 20 0 0 0 0.2 0.2 {}
T {@name} 20 -17.5 0 0 0.2 0.2 {}
]
C {lab_pin.sym} 50 -170 0 0 {name=p4 lab=AA embed=true}
[
v {xschem version=2.9.7 file_version=1.2}
G {type=label
format="*.alias @lab"
template="name=l1 sig_type=std_logic lab=xxx"}
V {}
S {}
E {}
B 5 -1.25 -1.25 1.25 1.25 {name=p dir=in}
T {@lab} -7.5 -8.125 0 1 0.33 0.33 {}
]
C {lab_pin.sym} 50 -110 0 0 {name=p5 lab=0 embed=true}
C {code_shown.sym} 580 -150 0 0 {name=STIMULI
only_toplevel=true
tclcommand="xschem edit_vi_prop"
value="
.tran 10n 10u uic
.save all
" embed=true}
[
v {xschem version=2.9.7 file_version=1.2}
G {type=netlist_commands
template="name=s1 only_toplevel=false value=blabla"
format="
@value
"}
V {}
S {}
E {}
L 4 0 -10 70 -10 {}
L 4 0 -10 0 10 {}
T {@name} 5 -25 0 0 0.3 0.3 {}
T {@value} 15 -5 0 0 0.3 0.3 {}
]
C {code.sym} 760 -170 0 0 {name=MODEL
only_toplevel=true
tclcommand="xschem edit_vi_prop"
value="************************************************
* NOMINAL N-Channel Transistor *
* UCB-3 Parameter Set *
* HIGH-SPEED CMOS Logic Family *
* 10-Jan.-1995 *
************************************************
.Model N NMOS (
+LEVEL = 3
+KP = 45.3E-6
+VTO = 0.72
+TOX = 51.5E-9
+NSUB = 2.8E15
+GAMMA = 0.94
+PHI = 0.65
+VMAX = 150E3
+RS = 40
+RD = 40
+XJ = 0.11E-6
+LD = 0.52E-6
+DELTA = 0.315
+THETA = 0.054
+ETA = 0.025
+KAPPA = 0.0
+WD = 0.0 )
***********************************************
* NOMINAL P-Channel transistor *
* UCB-3 Parameter Set *
* HIGH-SPEED CMOS Logic Family *
* 10-Jan.-1995 *
***********************************************
.Model P PMOS (
+LEVEL = 3
+KP = 22.1E-6
+VTO = -0.71
+TOX = 51.5E-9
+NSUB = 3.3E16
+GAMMA = 0.92
+PHI = 0.65
+VMAX = 970E3
+RS = 80
+RD = 80
+XJ = 0.63E-6
+LD = 0.23E-6
+DELTA = 2.24
+THETA = 0.108
+ETA = 0.322
+KAPPA = 0.0
+WD = 0.0 )
" embed=true}
[
v {xschem version=2.9.7 file_version=1.2}
G {type=netlist_commands
template="name=s1 only_toplevel=false value=blabla"
format="
@value
"}
V {}
S {}
E {}
L 4 20 30 60 30 {}
L 4 20 40 40 40 {}
L 4 20 50 60 50 {}
L 4 20 60 50 60 {}
L 4 20 70 50 70 {}
L 4 20 80 90 80 {}
L 4 20 90 40 90 {}
L 4 20 20 70 20 {}
L 4 20 10 40 10 {}
L 4 100 10 110 10 {}
L 4 110 10 110 110 {}
L 4 20 110 110 110 {}
L 4 20 100 20 110 {}
L 4 100 0 100 100 {}
L 4 10 100 100 100 {}
L 4 10 0 10 100 {}
L 4 10 0 100 0 {}
T {@name} 15 -25 0 0 0.3 0.3 {}
]
C {lab_pin.sym} 240 -230 0 0 {name=p6 lab=AA embed=true}
C {lab_pin.sym} 430 -230 0 1 {name=p7 lab=ZZ embed=true}
C {vsource.sym} 50 -240 0 0 {name=V2 value=3 embed=true}
C {lab_pin.sym} 50 -270 0 0 {name=p8 lab=VDD embed=true}
C {lab_pin.sym} 50 -210 0 0 {name=p9 lab=0 embed=true}
C {res.sym} 410 -170 0 0 {name=R1
value=20k
footprint=1206
device=resistor
m=1 embed=true}
[
v {xschem version=2.9.7 file_version=1.2}
G {type=resistor
format="@name @pinlist @value m=@m"
verilog_format="tran @name (@@P\\\\, @@M\\\\);"
tedax_format="footprint @name @footprint
value @name @value
device @name @device
@comptag"
template="name=R1
value=1k
footprint=1206
device=resistor
m=1"
}
V {}
S {}
E {}
L 4 0 20 0 30 {}
L 4 0 20 7.5 17.5 {}
L 4 -7.5 12.5 7.5 17.5 {}
L 4 -7.5 12.5 7.5 7.5 {}
L 4 -7.5 2.5 7.5 7.5 {}
L 4 -7.5 2.5 7.5 -2.5 {}
L 4 -7.5 -7.5 7.5 -2.5 {}
L 4 -7.5 -7.5 7.5 -12.5 {}
L 4 -7.5 -17.5 7.5 -12.5 {}
L 4 -7.5 -17.5 0 -20 {}
L 4 0 -30 0 -20 {}
L 4 2.5 -22.5 7.5 -22.5 {}
L 4 5 -25 5 -20 {}
B 5 -2.5 -32.5 2.5 -27.5 {name=P dir=inout propagate_to=1 pinnumber=1}
B 5 -2.5 27.5 2.5 32.5 {name=M dir=inout propagate_to=0 pinnumber=2}
T {@name} 15 -13.75 0 0 0.2 0.2 {}
T {@value} 15 1.25 0 0 0.2 0.2 {}
T {@#0:pinnumber} -10 -26.25 0 1 0.2 0.2 {layer=13}
T {@#1:pinnumber} -10 16.25 0 1 0.2 0.2 {layer=13}
]
C {lab_pin.sym} 410 -120 0 0 {name=p10 lab=HALF embed=true}
C {vsource.sym} 50 -340 0 0 {name=V3 value=1.5 embed=true}
C {lab_pin.sym} 50 -370 0 0 {name=p11 lab=HALF embed=true}
C {lab_pin.sym} 50 -310 0 0 {name=p12 lab=0 embed=true}
C {lab_pin.sym} 200 -530 0 0 {name=p13 lab=AA embed=true}
C {res.sym} 420 -470 0 0 {name=R2
value=20k
footprint=1206
device=resistor
m=1 embed=true}
C {lab_pin.sym} 420 -420 0 0 {name=p15 lab=HALF embed=true}
C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers" embed=true}
[
v {xschem version=2.9.7 file_version=1.2}
G {type=logo
template="name=l1 author=\\"Stefan Schippers\\""
verilog_ignore=true
vhdl_ignore=true
spice_ignore=true
tedax_ignore=true}
V {}
S {}
E {}
L 6 225 0 1020 0 {}
L 6 -160 0 -95 0 {}
T {@schname} 235 5 0 0 0.4 0.4 {}
T {@author} 235 -25 0 0 0.4 0.4 {}
T {@time_last_modified} 1020 -20 0 1 0.4 0.3 {}
T {SCHEM} 5 -25 0 0 1 1 {}
P 5 13 5 -30 -25 0 5 30 -15 30 -35 10 -55 30 -75 30 -45 0 -75 -30 -55 -30 -35 -10 -15 -30 5 -30 {fill=true}
]
C {cmos_inv.sch} 140 -300 0 0 {name=Xinv WN=15u WP=45u LLN=3u LLP=3u embed=true}
[
v {xschem version=2.9.7 file_version=1.2}
G {type=subcircuit
format="@name @pinlist @symname WN=@WN WP=@WP LLN=@LLN LLP=@LLP m=@m"
template="name=X1 WN=15u WP=45u LLN=3u LLP=3u m=1"
}
V {}
S {}
E {}
L 1 140 -260 140 -200 {lab=Z}
L 1 100 -290 100 -170 {lab=A}
L 1 60 -230 100 -230 {lab=A}
L 1 140 -230 190 -230 {lab=Z}
L 1 140 -340 140 -320 {lab=VDD}
L 1 140 -140 140 -120 {lab=0}
L 4 125 -200 125 -140 {}
L 4 125 -190 140 -190 {}
L 4 140 -200 140 -190 {}
L 4 125 -150 140 -150 {}
L 4 140 -150 140 -140 {}
L 4 115 -185 115 -155 {}
L 4 115 -170 115 -165 {}
L 4 100 -170 107.5 -170 {}
L 4 100 -170 115 -170 {}
L 4 130 -170 140 -170 {}
L 4 125 -175 130 -170 {}
L 4 125 -165 130 -170 {}
L 4 125 -320 125 -260 {11}
L 4 125 -270 140 -270 {}
L 4 140 -270 140 -260 {}
L 4 125 -310 140 -310 {}
L 4 140 -320 140 -310 {}
L 4 115 -305 115 -275 {}
L 4 115 -295 115 -290 {}
L 4 112.5 -295 115 -292.5 {}
L 4 110 -295 112.5 -295 {}
L 4 107.5 -292.5 110 -295 {}
L 4 107.5 -292.5 107.5 -287.5 {}
L 4 107.5 -287.5 110 -285 {}
L 4 110 -285 112.5 -285 {}
L 4 112.5 -285 115 -287.5 {}
L 4 100 -290 107.5 -290 {}
L 4 130 -290 140 -290 {}
L 4 125 -295 130 -290 {}
L 4 125 -285 130 -290 {}
L 4 140 -360 140 -340 {}
L 4 130 -360 150 -360 {}
L 7 70 -232.5 72.5 -230 {}
L 7 70 -227.5 72.5 -230 {}
L 7 177.5 -232.5 180 -230 {}
L 7 177.5 -227.5 180 -230 {}
B 5 57.5 -232.5 62.5 -227.5 {name=A dir=in }
B 5 187.5 -232.5 192.5 -227.5 {name=Z dir=out }
B 7 137.5 -202.5 142.5 -197.5 {name=d dir=inout}
B 7 97.5 -172.5 102.5 -167.5 {name=g dir=in}
B 7 137.5 -142.5 142.5 -137.5 {name=s dir=inout}
B 7 137.5 -172.5 142.5 -167.5 {name=b dir=in}
B 7 137.5 -262.5 142.5 -257.5 {name=d dir=inout}
B 7 97.5 -292.5 102.5 -287.5 {name=g dir=in}
B 7 137.5 -322.5 142.5 -317.5 {name=s dir=inout}
B 7 137.5 -292.5 142.5 -287.5 {name=b dir=in}
B 7 137.5 -342.5 142.5 -337.5 {name=p dir=inout verilog_type=wire}
B 7 138.75 -121.25 141.25 -118.75 {name=p dir=in}
B 7 138.75 -171.25 141.25 -168.75 {name=p dir=in}
B 7 138.75 -291.25 141.25 -288.75 {name=p dir=in}
T {@name} 60 -405 0 0 0.2 0.2 {}
T {@symname} 63.75 -85 0 0 0.2 0.2 {}
T {$WN\\/$LLN\\/$1} 127.5 -188.75 0 0 0.2 0.2 {}
T {$M1} 127.5 -163.75 0 0 0.2 0.2 {}
T {D} 145 -197.5 0 0 0.15 0.15 {}
T {$WP\\/$LLP\\/$1} 127.5 -307.5 0 0 0.2 0.2 {}
T {$M2} 127.5 -283.75 0 0 0.2 0.2 {}
T {D} 145 -270 0 0 0.15 0.15 {}
T {$VDD} 127.5 -375 0 0 0.2 0.2 {}
T {$0} 132.5 -128.125 0 1 0.33 0.33 {}
T {$A} 63.75 -246.25 0 0 0.2 0.2 {}
T {$Z} 186.25 -246.25 0 1 0.2 0.2 {}
T {$0} 147.5 -178.125 0 0 0.33 0.33 {}
T {$VDD} 147.5 -298.125 0 0 0.33 0.33 {}
P 4 5 60 -390 60 -90 190 -90 190 -390 60 -390 {}
]
C {cmos_inv.sym} 280 -230 0 0 {name=Xinv2 WN=15u WP=45u LLN=3u LLP=3u embed=true}
[
v {xschem version=2.9.7 file_version=1.2}
G {type=subcircuit
format="@name @pinlist @symname WN=@WN WP=@WP LLN=@LLN LLP=@LLP m=@m"
verilog_primitive=true
verilog_format="assign #80 @@Z = ~ @@A ;"
template="name=X1 WN=15u WP=45u LLN=3u LLP=3u m=1"
}
V {}
S {}
E {}
L 4 -40 0 -27.5 0 {}
L 4 -27.5 -20 -27.5 20 {}
L 4 -27.5 -20 16.25 0 {}
L 4 -27.5 20 16.25 0 {}
L 4 26.25 0 40 0 {}
B 5 -42.5 -2.5 -37.5 2.5 {name=A dir=in }
B 5 37.5 -2.5 42.5 2.5 {name=Z dir=out }
A 4 21.25 -0 5 180 360 {}
T {@name} -26.25 -5 0 0 0.2 0.2 {}
T {@symname} -26.25 35 0 0 0.2 0.2 {}
T {@WP\\/@LLP\\/@m} -16.25 -25 0 0 0.2 0.2 {}
T {@WN\\/@LLN\\/@m} -16.25 15 0 0 0.2 0.2 {}
]
C {bus_keeper.sch} 1200 60 0 0 {name=Xkeeper WN_FB=3u WP_FB=5u embed=true}
[
v {xschem version=2.9.7 file_version=1.2}
G {type=subcircuit
format="@name @pinlist @symname WN_FB=@WN_FB WP_FB=@WP_FB"
template="name=X1 WN_FB=1u WP_FB=2u"}
V {}
S {}
E {}
L 1 250 -300 300 -300 {lab=A}
L 1 280 -680 300 -680 {lab=A}
L 1 280 -680 280 -300 {lab=A}
L 1 430 -300 450 -300 {lab=#net1}
L 1 450 -680 450 -300 {lab=#net1}
L 1 430 -680 450 -680 {lab=#net1}
L 1 380 -330 380 -270 {lab=Z}
L 1 340 -360 340 -240 {lab=A}
L 1 300 -300 340 -300 {lab=A}
L 1 380 -300 430 -300 {lab=Z}
L 1 380 -410 380 -390 {lab=VDD}
L 1 380 -210 380 -190 {lab=0}
L 1 350 -710 350 -650 {lab=Z}
L 1 390 -740 390 -620 {lab=A}
L 1 390 -680 430 -680 {lab=A}
L 1 300 -680 350 -680 {lab=Z}
L 1 350 -790 350 -770 {lab=VDD}
L 1 350 -590 350 -570 {lab=0}
L 4 365 -270 365 -210 {}
L 4 365 -260 380 -260 {}
L 4 380 -270 380 -260 {}
L 4 365 -220 380 -220 {}
L 4 380 -220 380 -210 {}
L 4 355 -255 355 -225 {}
L 4 355 -240 355 -235 {}
L 4 340 -240 347.5 -240 {}
L 4 340 -240 355 -240 {}
L 4 370 -240 380 -240 {}
L 4 365 -245 370 -240 {}
L 4 365 -235 370 -240 {}
L 4 365 -390 365 -330 {11}
L 4 365 -340 380 -340 {}
L 4 380 -340 380 -330 {}
L 4 365 -380 380 -380 {}
L 4 380 -390 380 -380 {}
L 4 355 -375 355 -345 {}
L 4 355 -365 355 -360 {}
L 4 352.5 -365 355 -362.5 {}
L 4 350 -365 352.5 -365 {}
L 4 347.5 -362.5 350 -365 {}
L 4 347.5 -362.5 347.5 -357.5 {}
L 4 347.5 -357.5 350 -355 {}
L 4 350 -355 352.5 -355 {}
L 4 352.5 -355 355 -357.5 {}
L 4 340 -360 347.5 -360 {}
L 4 370 -360 380 -360 {}
L 4 365 -365 370 -360 {}
L 4 365 -355 370 -360 {}
L 4 380 -430 380 -410 {}
L 4 370 -430 390 -430 {}
L 4 365 -650 365 -590 {}
L 4 350 -640 365 -640 {}
L 4 350 -650 350 -640 {}
L 4 350 -600 365 -600 {}
L 4 350 -600 350 -590 {}
L 4 375 -635 375 -605 {}
L 4 375 -620 375 -615 {}
L 4 382.5 -620 390 -620 {}
L 4 375 -620 390 -620 {}
L 4 350 -620 360 -620 {}
L 4 360 -620 365 -625 {}
L 4 360 -620 365 -615 {}
L 4 365 -770 365 -710 {11}
L 4 350 -720 365 -720 {}
L 4 350 -720 350 -710 {}
L 4 350 -760 365 -760 {}
L 4 350 -770 350 -760 {}
L 4 375 -755 375 -725 {}
L 4 375 -745 375 -740 {}
L 4 375 -742.5 377.5 -745 {}
L 4 377.5 -745 380 -745 {}
L 4 380 -745 382.5 -742.5 {}
L 4 382.5 -742.5 382.5 -737.5 {}
L 4 380 -735 382.5 -737.5 {}
L 4 377.5 -735 380 -735 {}
L 4 375 -737.5 377.5 -735 {}
L 4 382.5 -740 390 -740 {}
L 4 350 -740 360 -740 {}
L 4 360 -740 365 -745 {}
L 4 360 -740 365 -735 {}
L 4 350 -810 350 -790 {}
L 4 340 -810 360 -810 {}
L 7 310 -302.5 312.5 -300 {}
L 7 310 -297.5 312.5 -300 {}
L 7 417.5 -302.5 420 -300 {}
L 7 417.5 -297.5 420 -300 {}
L 7 417.5 -680 420 -682.5 {}
L 7 417.5 -680 420 -677.5 {}
L 7 310 -680 312.5 -682.5 {}
L 7 310 -680 312.5 -677.5 {}
L 7 257.5 -300 260 -302.5 {}
L 7 257.5 -300 260 -297.5 {}
L 7 260 -302.5 262.5 -300 {}
L 7 260 -297.5 262.5 -300 {}
B 5 247.5 -302.5 252.5 -297.5 {name=A dir=inout }
B 7 377.5 -272.5 382.5 -267.5 {name=d dir=inout}
B 7 337.5 -242.5 342.5 -237.5 {name=g dir=in}
B 7 377.5 -212.5 382.5 -207.5 {name=s dir=inout}
B 7 377.5 -242.5 382.5 -237.5 {name=b dir=in}
B 7 377.5 -332.5 382.5 -327.5 {name=d dir=inout}
B 7 337.5 -362.5 342.5 -357.5 {name=g dir=in}
B 7 377.5 -392.5 382.5 -387.5 {name=s dir=inout}
B 7 377.5 -362.5 382.5 -357.5 {name=b dir=in}
B 7 377.5 -412.5 382.5 -407.5 {name=p dir=inout verilog_type=wire}
B 7 378.75 -191.25 381.25 -188.75 {name=p dir=in}
B 7 297.5 -302.5 302.5 -297.5 {}
B 7 427.5 -302.5 432.5 -297.5 {}
B 7 378.75 -241.25 381.25 -238.75 {name=p dir=in}
B 7 378.75 -361.25 381.25 -358.75 {name=p dir=in}
B 7 347.5 -652.5 352.5 -647.5 {name=d dir=inout}
B 7 387.5 -622.5 392.5 -617.5 {name=g dir=in}
B 7 347.5 -592.5 352.5 -587.5 {name=s dir=inout}
B 7 347.5 -622.5 352.5 -617.5 {name=b dir=in}
B 7 347.5 -712.5 352.5 -707.5 {name=d dir=inout}
B 7 387.5 -742.5 392.5 -737.5 {name=g dir=in}
B 7 347.5 -772.5 352.5 -767.5 {name=s dir=inout}
B 7 347.5 -742.5 352.5 -737.5 {name=b dir=in}
B 7 347.5 -792.5 352.5 -787.5 {name=p dir=inout verilog_type=wire}
B 7 348.75 -571.25 351.25 -568.75 {name=p dir=in}
B 7 427.5 -682.5 432.5 -677.5 {}
B 7 297.5 -682.5 302.5 -677.5 {}
B 7 348.75 -621.25 351.25 -618.75 {name=p dir=in}
B 7 348.75 -741.25 351.25 -738.75 {name=p dir=in}
T {@name} 250 -915 0 0 0.5 0.5 {}
T {@symname} 253.75 -115 0 0 0.5 0.5 {}
T {$X2} 300 -475 0 0 0.2 0.2 {}
T {cmos_inv} 303.75 -155 0 0 0.2 0.2 {}
T {$15u\\/$3u\\/$1} 367.5 -258.75 0 0 0.2 0.2 {}
T {$M1} 367.5 -233.75 0 0 0.2 0.2 {}
T {D} 385 -267.5 0 0 0.15 0.15 {}
T {$45u\\/$3u\\/$1} 367.5 -377.5 0 0 0.2 0.2 {}
T {$M2} 367.5 -353.75 0 0 0.2 0.2 {}
T {D} 385 -340 0 0 0.15 0.15 {}
T {$VDD} 367.5 -445 0 0 0.2 0.2 {}
T {$0} 372.5 -198.125 0 1 0.33 0.33 {}
T {$A} 303.75 -316.25 0 0 0.2 0.2 {}
T {$Z} 426.25 -316.25 0 1 0.2 0.2 {}
T {$0} 387.5 -248.125 0 0 0.33 0.33 {}
T {$VDD} 387.5 -368.125 0 0 0.33 0.33 {}
T {$X1} 430 -855 0 1 0.2 0.2 {}
T {cmos_inv} 426.25 -535 0 1 0.2 0.2 {}
T {$WN_FB\\/$3u\\/$1} 362.5 -638.75 0 1 0.2 0.2 {}
T {$M1} 362.5 -613.75 0 1 0.2 0.2 {}
T {D} 345 -647.5 0 1 0.15 0.15 {}
T {$WP_FB\\/$3u\\/$1} 362.5 -757.5 0 1 0.2 0.2 {}
T {$M2} 362.5 -733.75 0 1 0.2 0.2 {}
T {D} 345 -720 0 1 0.15 0.15 {}
T {$VDD} 362.5 -825 0 1 0.2 0.2 {}
T {$0} 357.5 -578.125 0 0 0.33 0.33 {}
T {$A} 426.25 -696.25 0 1 0.2 0.2 {}
T {$Z} 303.75 -696.25 0 0 0.2 0.2 {}
T {$0} 342.5 -628.125 0 1 0.33 0.33 {}
T {$VDD} 342.5 -748.125 0 1 0.33 0.33 {}
T {$A} 253.75 -316.25 0 0 0.2 0.2 {}
P 4 5 250 -880 250 -120 480 -120 480 -880 250 -880 {}
P 4 5 300 -460 300 -160 430 -160 430 -460 300 -460 {}
P 4 5 430 -840 430 -540 300 -540 300 -840 430 -840 {}
]
C {lab_pin.sym} 700 -530 0 1 {name=p1 lab=Z embed=true}

View File

@ -1,134 +0,0 @@
v {xschem version=2.9.7 file_version=1.2}
G {}
K {type=subcircuit
format="@name @pinlist @symname WN_FB=@WN_FB WP_FB=@WP_FB"
template="name=X1 WN_FB=3u WP_FB=4u"}
V {}
S {}
E {}
P 4 5 250 -880 250 -120 480 -120 480 -880 250 -880 {}
T {@name} 250 -915 0 0 0.5 0.5 {}
T {@symname} 253.75 -115 0 0 0.5 0.5 {}
N 250 -300 300 -300 {lab=A}
N 280 -680 300 -680 {lab=A}
N 280 -680 280 -300 {lab=A}
N 430 -300 450 -300 {lab=#net1}
N 450 -680 450 -300 {lab=#net1}
N 430 -680 450 -680 {lab=#net1}
C {cmos_inv.sch} 240 -70 0 0 {name=X2 WN=15u WP=45u LLN=3u LLP=3u embed=true}
[
v {xschem version=2.9.7 file_version=1.2}
G {type=subcircuit
format="@name @pinlist @symname WN=@WN WP=@WP LLN=@LLN LLP=@LLP"
template="name=X1 WN=15u WP=45u LLN=3u LLP=3u"
}
V {}
S {}
E {}
L 1 140 -260 140 -200 {lab=Z}
L 1 100 -290 100 -170 {lab=A}
L 1 60 -230 100 -230 {lab=A}
L 1 140 -230 190 -230 {lab=Z}
L 1 140 -340 140 -320 {lab=VDD}
L 1 140 -140 140 -120 {lab=0}
L 4 125 -200 125 -140 {}
L 4 125 -190 140 -190 {}
L 4 140 -200 140 -190 {}
L 4 125 -150 140 -150 {}
L 4 140 -150 140 -140 {}
L 4 115 -185 115 -155 {}
L 4 115 -170 115 -165 {}
L 4 100 -170 107.5 -170 {}
L 4 100 -170 115 -170 {}
L 4 130 -170 140 -170 {}
L 4 125 -175 130 -170 {}
L 4 125 -165 130 -170 {}
L 4 125 -320 125 -260 {11}
L 4 125 -270 140 -270 {}
L 4 140 -270 140 -260 {}
L 4 125 -310 140 -310 {}
L 4 140 -320 140 -310 {}
L 4 115 -305 115 -275 {}
L 4 115 -295 115 -290 {}
L 4 112.5 -295 115 -292.5 {}
L 4 110 -295 112.5 -295 {}
L 4 107.5 -292.5 110 -295 {}
L 4 107.5 -292.5 107.5 -287.5 {}
L 4 107.5 -287.5 110 -285 {}
L 4 110 -285 112.5 -285 {}
L 4 112.5 -285 115 -287.5 {}
L 4 100 -290 107.5 -290 {}
L 4 130 -290 140 -290 {}
L 4 125 -295 130 -290 {}
L 4 125 -285 130 -290 {}
L 4 140 -360 140 -340 {}
L 4 130 -360 150 -360 {}
L 7 70 -232.5 72.5 -230 {}
L 7 70 -227.5 72.5 -230 {}
L 7 177.5 -232.5 180 -230 {}
L 7 177.5 -227.5 180 -230 {}
B 5 57.5 -232.5 62.5 -227.5 {name=A dir=in}
B 5 187.5 -232.5 192.5 -227.5 {name=Z dir=out}
B 7 137.5 -202.5 142.5 -197.5 {name=d dir=inout}
B 7 97.5 -172.5 102.5 -167.5 {name=g dir=in}
B 7 137.5 -142.5 142.5 -137.5 {name=s dir=inout}
B 7 137.5 -172.5 142.5 -167.5 {name=b dir=in}
B 7 137.5 -262.5 142.5 -257.5 {name=d dir=inout}
B 7 97.5 -292.5 102.5 -287.5 {name=g dir=in}
B 7 137.5 -322.5 142.5 -317.5 {name=s dir=inout}
B 7 137.5 -292.5 142.5 -287.5 {name=b dir=in}
B 7 137.5 -342.5 142.5 -337.5 {name=p dir=inout verilog_type=wire}
B 7 138.75 -121.25 141.25 -118.75 {name=p dir=in}
B 7 138.75 -171.25 141.25 -168.75 {name=p dir=in}
B 7 138.75 -291.25 141.25 -288.75 {name=p dir=in}
T {@name} 60 -405 0 0 0.2 0.2 {}
T {@symname} 63.75 -85 0 0 0.2 0.2 {}
T { WN\\/ LLN\\/ 1} 127.5 -188.75 0 0 0.2 0.2 {}
T { M1} 127.5 -163.75 0 0 0.2 0.2 {}
T {D} 145 -197.5 0 0 0.15 0.15 {}
T { WP\\/ LLP\\/ 1} 127.5 -307.5 0 0 0.2 0.2 {}
T { M2} 127.5 -283.75 0 0 0.2 0.2 {}
T {D} 145 -270 0 0 0.15 0.15 {}
T { VDD} 127.5 -375 0 0 0.2 0.2 {}
T { 0} 132.5 -128.125 0 1 0.33 0.33 {}
T { A} 63.75 -246.25 0 0 0.2 0.2 {}
T { Z} 186.25 -246.25 0 1 0.2 0.2 {}
T { 0} 147.5 -178.125 0 0 0.33 0.33 {}
T { VDD} 147.5 -298.125 0 0 0.33 0.33 {}
P 4 5 60 -390 60 -90 190 -90 190 -390 60 -390 {}
]
C {cmos_inv.sch} 490 -450 0 1 {name=X1 WN=WN_FB WP=WP_FB LLN=3u LLP=3u embed=true}
C {iopin.sym} 250 -300 0 1 {name=p1 lab=A embed=true}
[
v {xschem version=2.9.7 file_version=1.2}
G {type=iopin
format="*.iopin @lab"
template="name=p1 lab=xxx"
}
V {}
S {}
E {}
B 5 -0.0098 -0.009765619999999999 0.0098 0.009765619999999999 {name=p dir=inout}
T {@lab} 19.8438 -8.75 0 0 0.4 0.33 {}
P 5 7 0 0 5.625 -4.84375 10.7812 -4.84375 16.4062 -0 10.7812 4.84375 5.625 4.84375 -0 0 {fill=true}
]
C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers" embed=true}
[
v {xschem version=2.9.7 file_version=1.2}
G {type=logo
template="name=l1 author=\\"Stefan Schippers\\""
verilog_ignore=true
vhdl_ignore=true
spice_ignore=true
tedax_ignore=true}
V {}
S {}
E {}
L 6 225 0 1020 0 {}
L 6 -160 0 -95 0 {}
T {@schname} 235 5 0 0 0.4 0.4 {}
T {@author} 235 -25 0 0 0.4 0.4 {}
T {@time_last_modified} 1020 -20 0 1 0.4 0.3 {}
T {SCHEM} 5 -25 0 0 1 1 {}
P 5 13 5 -30 -25 0 5 30 -15 30 -35 10 -55 30 -75 30 -45 0 -75 -30 -55 -30 -35 -10 -15 -30 5 -30 {fill=true}
]

View File

@ -1,360 +0,0 @@
v {xschem version=2.9.7 file_version=1.2}
G {}
V {// test}
S {* test}
E {}
T {rrreal type:
-----------
rreal is a record type containing voltage value, drive strength and
capacitive loading of an electrical node.
rrreal is a resolved subtype of rreal.
The resolution function invoked by the simulator updates
voltages, strengths and capacitive loading of all nodes.
this allows to simulate voltage transients, charge sharing,
floating conditions and more.
the example uses bidirectional analog switches
and simulates charge pumps which have a finite
driving capability (output impedance)} 10 -410 0 0 0.3 0.3 {}
T {VHDL DESIGN EXAMPLE} 140 -1290 0 0 1 1 {}
T {set netlist mode to VHDL
- create netlist
- simulate with ghdl
- view waveforms} 110 -1200 0 0 0.6 0.6 {}
N 830 -680 900 -680 {lab=VXS}
N 450 -680 510 -680 {lab=VX}
N 450 -680 450 -570 {lab=VX}
N 1230 -680 1240 -680 {lab=SP}
N 340 -680 450 -680 {lab=VX}
N 830 -680 830 -570 {lab=VXS}
N 1230 -680 1230 -570 {lab=SP}
N 470 -800 480 -800 {lab=VX2}
N 840 -800 840 -680 {lab=VXS}
N 780 -800 840 -800 {lab=VXS}
N 350 -910 470 -910 {lab=VX2}
N 470 -910 470 -800 {lab=VX2}
N 810 -680 830 -680 {lab=VXS}
N 1200 -680 1230 -680 {lab=SP}
N 340 -800 470 -800 {lab=VX2}
C {code.sym} 600 -200 0 0 {name=CODE
vhdl_ignore=false
value="
-- these assignments are done to have the voltage values available
-- in the waveform file
V_VX <= VX.value;
V_VX2 <= VX2.value;
V_VXS <= VXS.value;
V_SP <= SP.value;
process
begin
ING<='0';
ING1<='0';
SW <= '0';
SW1<='0';
SW2<='0';
--VX <= rreal'(4.5,10.0,0.0);
--VX2 <= rreal'(3.0, 5.0, 0.0);
wait for 200 ns;
ING1<='1';
wait for 200 ns;
ING<='1';
wait for 200 ns;
SW<='1';
wait for 200 ns;
SW2<='1';
wait for 200 ns;
SW1<='1';
wait for 200 ns;
SW1<='0';
wait for 200 ns;
SW2<='0';
wait for 200 ns;
SW1<='1';
wait for 200 ns;
SW<='1';
wait for 200 ns;
ING <='0';
wait for 200 ns;
SW1<= '0';
wait for 200 ns;
SW<='1';
wait for 200 ns;
ING<='1';
wait for 200 ns;
SW <= '0';
wait for 200 ns;
SW1<= '1';
wait for 200 ns;
ING<='1';
wait for 200 ns;
SW<='0';
wait for 200 ns;
SW1<='0';
wait for 200 ns;
SW<='1';
wait for 200 ns;
SW1<='1';
wait for 200 ns;
SW1<='0';
wait for 200 ns;
SW1<='1';
wait for 200 ns;
wait;
end process;
"
}
C {use.sym} 840 -220 0 0 {library ieee;
use std.TEXTIO.all;
use ieee.std_logic_1164.all;
library work;
use work.rrreal.all;
}
C {pump.sym} 250 -680 0 0 {name=x4 conduct="1.0/20000.0" val=4.5}
C {lab_pin.sym} 150 -680 0 0 {name=l4 lab=ING}
C {switch_rreal.sch} 660 -670 0 0 {name=x5 del="2 ns"}
C {lab_pin.sym} 510 -660 0 0 {name=l5 lab=SW}
C {real_capa.sym} 450 -540 0 0 {name=x3 cap=30.0}
C {real_capa.sym} 830 -540 0 0 {name=x1 cap=100.0}
C {switch_rreal.sch} 1050 -670 0 0 {name=x2 del="2 ns"}
C {lab_pin.sym} 900 -660 0 0 {name=l2 lab=SW1}
C {lab_pin.sym} 1240 -680 0 1 {name=l3 lab=SP sig_type=rrreal}
C {real_capa.sym} 1230 -540 0 0 {name=x6 cap=20.0}
C {lab_wire.sym} 860 -680 0 1 {name=l6 lab=VXS sig_type=rrreal
}
C {pump.sym} 250 -800 0 0 {name=x7 conduct="1.0/40000.0" val=3.0}
C {lab_pin.sym} 150 -800 0 0 {name=l7 lab=ING1}
C {switch_rreal.sym} 630 -790 0 0 {name=x8 del="2 ns"}
C {lab_pin.sym} 480 -780 0 0 {name=l0 lab=SW2}
C {lab_wire.sym} 400 -800 0 1 {name=l8 lab=VX2 sig_type=rrreal
}
C {real_capa.sym} 350 -880 0 0 {name=x9 cap=40.0}
C {package_not_shown.sym} 830 -340 0 0 {
library ieee, std;
use std.textio.all;
package rrreal is
type rreal is
record
value : real;
conduct : real;
cap : real;
end record;
type rreal_vector is array (natural range <>) of rreal;
function resolved_real( r: rreal_vector ) return rreal;
procedure print(s : in string);
subtype rrreal is resolved_real rreal;
type rrreal_vector is array (natural range <>) of rrreal;
CONSTANT RREAL_X : rreal := rreal'(value=> 0.0, cap=>0.0, conduct=>-1.0);
CONSTANT RREAL_Z : rreal := rreal'(value=> 0.0, cap=>0.0, conduct=>0.0);
CONSTANT RREAL_0 : rreal := rreal'(value=> 0.0, cap=>0.0, conduct=>10.0);
CONSTANT REAL_Z : real := 20.0;
CONSTANT REAL_X : real := 20.0;
procedure transition(
signal sig: INOUT rreal;
constant endval: IN real;
constant del: IN time
);
procedure glitch(
signal sig: INOUT rreal;
constant lowval: IN real;
constant endval: IN real;
constant del: IN time
);
end rrreal; -- end package declaration
package body rrreal is
procedure print(s : in string) is
variable outbuf: line;
begin
write(outbuf, s);
writeline(output, outbuf);
end procedure;
-- function resolved_real( r:rreal_vector) return rreal is
-- VARIABLE result : rreal := RREAL_Z;
-- begin
-- IF (r'LENGTH = 1) THEN RETURN r(r'LOW);
-- ELSE
-- FOR i IN r'RANGE LOOP
-- result.cap := result.cap + r(i).cap ;
-- IF r(i).value /=REAL_Z THEN
-- IF result.value /=REAL_Z THEN
-- result.value := REAL_X ;
-- ELSE
-- result.value := r(i).value ;
-- END IF;
-- END IF ;
-- END LOOP;
-- END IF;
-- RETURN result;
-- end resolved_real;
function resolved_real( r:rreal_vector) return rreal is
VARIABLE result : rreal := RREAL_Z;
variable vcapshare : real := 0.0;
begin
IF (r'LENGTH = 1) THEN RETURN r(r'LOW);
ELSE
FOR i IN r'RANGE LOOP
if r(i).conduct = -1.0 then
result := RREAL_X;
exit;
end if;
-- only process initialized (valid) data
if r(i).value > -30.0 and r(i).value < 30.0 then
if r(i).cap > -1.0e12 and r(i).cap < 1.0e12 then
if r(i).conduct > -1.0e12 and r(i).conduct < 1.0e12 then
vcapshare := vcapshare + r(i).value * r(i).cap;
result.value := result.value + r(i).value * r(i).conduct;
result.cap := result.cap + r(i).cap ;
if(r(i).conduct > 0.0 ) then
-- result.conduct := result.conduct + 1.0/r(i).conduct ;
result.conduct := result.conduct + r(i).conduct ;
end if;
end if;
end if;
end if;
END LOOP;
END IF;
if result.conduct /= 0.0 then
result.value := result.value / result.conduct ; -- conductance
-- result.value := result.value * result.conduct ; -- resistance
-- result.conduct := 1.0 / result.conduct;
elsif result.cap >0.0 then
result.value := vcapshare / result.cap;
else
result.value:=0.0;
end if;
RETURN result;
end resolved_real;
procedure transition(
signal sig: INOUT rreal;
constant endval: IN real;
constant del: IN time) is
variable step: real;
variable startval: real;
variable del2: time;
begin
del2 := del;
if del2 = 0 fs then
del2 := 1 ns;
end if;
startval := sig.value;
step := (endval-startval);
if abs(endval-startval) < 0.01 then --do not propagate events if endval very close to startval
return;
end if;
-- sig.value <= endval after del;
sig.value <= startval,
startval+0.25*step after del2*0.1,
startval+0.45*step after del2*0.2,
startval+0.60*step after del2*0.3,
startval+0.72*step after del2*0.4,
startval+0.80*step after del2*0.5,
startval+0.86*step after del2*0.6,
startval+0.90*step after del2*0.7,
startval+0.94*step after del2*0.8,
startval+0.97*step after del2*0.9,
endval after del2;
end transition;
procedure glitch(
signal sig: INOUT rreal;
constant lowval: IN real;
constant endval: IN real;
constant del: IN time) is
variable step: real;
variable step2: real;
variable startval: real;
variable del2 : time;
begin
del2 := del;
if del2 = 0 fs then
del2 := 1 ns;
end if;
startval := sig.value;
step := (lowval-startval);
step2 := (lowval-endval);
if abs(lowval-startval) < 0.01 then --do not propagate events if endval very close to startval
return;
end if;
sig.value <=
-- startval,
-- startval+0.25*step after del*0.05,
-- startval+0.45*step after del*0.1,
-- startval+0.60*step after del*0.15,
-- startval+0.72*step after del*0.2,
-- startval+0.80*step after del*0.25,
-- startval+0.86*step after del*0.3,
-- startval+0.90*step after del*0.35,
-- startval+0.94*step after del*0.4,
-- startval+0.97*step after del*0.45,
-- lowval after del*0.5,
-- lowval-0.25*step2 after del*0.55,
-- lowval-0.45*step2 after del*0.6,
-- lowval-0.60*step2 after del*0.65,
-- lowval-0.72*step2 after del*0.7,
-- lowval-0.80*step2 after del*0.75,
-- lowval-0.86*step2 after del*0.8,
-- lowval-0.90*step2 after del*0.85,
-- lowval-0.94*step2 after del*0.9,
-- lowval-0.97*step2 after del*0.95,
-- endval after del;
lowval,
lowval-0.25*step2 after del2*0.1,
lowval-0.45*step2 after del2*0.2,
lowval-0.60*step2 after del2*0.3,
lowval-0.72*step2 after del2*0.4,
lowval-0.80*step2 after del2*0.5,
lowval-0.86*step2 after del2*0.6,
lowval-0.90*step2 after del2*0.7,
lowval-0.94*step2 after del2*0.8,
lowval-0.97*step2 after del2*0.9,
endval after del2;
end glitch;
end rrreal; -- end package body
}
C {title.sym} 160 -40 0 0 {name=l9 author="Stefan Schippers"}
C {arch_declarations.sym} 830 -280 0 0 {
signal V_VX, V_VX2, V_VXS, V_SP: real;
}
C {lab_wire.sym} 430 -680 0 1 {name=l1 lab=VX sig_type=rrreal }

View File

@ -1,619 +0,0 @@
v {xschem version=2.9.7 file_version=1.2}
G {}
V {// test}
S {* test}
E {}
T {rrreal type:
-----------
rreal is a record type containing voltage value, drive strength and
capacitive loading of an electrical node.
rrreal is a resolved subtype of rreal.
The resolution function invoked by the simulator updates
voltages, strengths and capacitive loading of all nodes.
this allows to simulate voltage transients, charge sharing,
floating conditions and more.
the example uses bidirectional analog switches
and simulates charge pumps which have a finite
driving capability (output impedance)} 10 -410 0 0 0.3 0.3 {}
T {VHDL DESIGN EXAMPLE} 140 -1290 0 0 1 1 {}
T {set netlist mode to VHDL
- create netlist
- simulate with ghdl
- view waveforms} 110 -1200 0 0 0.6 0.6 {}
N 830 -680 900 -680 {lab=VXS}
N 450 -680 510 -680 {lab=VX}
N 450 -680 450 -570 {lab=VX}
N 1230 -680 1240 -680 {lab=SP}
N 340 -680 450 -680 {lab=VX}
N 830 -680 830 -570 {lab=VXS}
N 1230 -680 1230 -570 {lab=SP}
N 470 -800 480 -800 {lab=VX2}
N 810 -800 810 -680 {lab=VXS}
N 780 -800 810 -800 {lab=VXS}
N 350 -910 470 -910 {lab=VX2}
N 470 -910 470 -800 {lab=VX2}
N 810 -680 830 -680 {lab=VXS}
N 1200 -680 1230 -680 {lab=SP}
N 340 -800 470 -800 {lab=VX2}
C {code.sym} 600 -200 0 0 {name=CODE
vhdl_ignore=false
value="
-- these assignments are done to have the voltage values available
-- in the waveform file
V_VX <= VX.value;
V_VX2 <= VX2.value;
V_VXS <= VXS.value;
V_SP <= SP.value;
process
begin
ING<='0';
ING1<='0';
SW <= '0';
SW1<='0';
SW2<='0';
--VX <= rreal'(4.5,10.0,0.0);
--VX2 <= rreal'(3.0, 5.0, 0.0);
wait for 200 ns;
ING1<='1';
wait for 200 ns;
ING<='1';
wait for 200 ns;
SW<='1';
wait for 200 ns;
SW2<='1';
wait for 200 ns;
SW1<='1';
wait for 200 ns;
SW1<='0';
wait for 200 ns;
SW2<='0';
wait for 200 ns;
SW1<='1';
wait for 200 ns;
SW<='1';
wait for 200 ns;
ING <='0';
wait for 200 ns;
SW1<= '0';
wait for 200 ns;
SW<='1';
wait for 200 ns;
ING<='1';
wait for 200 ns;
SW <= '0';
wait for 200 ns;
SW1<= '1';
wait for 200 ns;
ING<='1';
wait for 200 ns;
SW<='0';
wait for 200 ns;
SW1<='0';
wait for 200 ns;
SW<='1';
wait for 200 ns;
SW1<='1';
wait for 200 ns;
SW1<='0';
wait for 200 ns;
SW1<='1';
wait for 200 ns;
wait;
end process;
"
embed=true}
[
v {xschem version=2.9.7 file_version=1.2}
G {type=netlist_commands
template="name=s1 only_toplevel=false value=blabla"
format="
@value
"}
V {}
S {}
E {}
L 4 20 30 60 30 {}
L 4 20 40 40 40 {}
L 4 20 50 60 50 {}
L 4 20 60 50 60 {}
L 4 20 70 50 70 {}
L 4 20 80 90 80 {}
L 4 20 90 40 90 {}
L 4 20 20 70 20 {}
L 4 20 10 40 10 {}
L 4 100 10 110 10 {}
L 4 110 10 110 110 {}
L 4 20 110 110 110 {}
L 4 20 100 20 110 {}
L 4 100 0 100 100 {}
L 4 10 100 100 100 {}
L 4 10 0 10 100 {}
L 4 10 0 100 0 {}
T {@name} 15 -25 0 0 0.3 0.3 {}
]
C {use.sym} 840 -220 0 0 {library ieee;
use std.TEXTIO.all;
use ieee.std_logic_1164.all;
library work;
use work.rrreal.all;
-- embed=true}
[
v {xschem version=2.9.7 file_version=1.2}
G {type=use
template="
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
"}
V {}
S {}
E {}
L 4 -0 -10 355 -10 {}
T {VHDL USE} 5 -25 0 0 0.3 0.3 {}
T {@prop_ptr} 45 5 0 0 0.2 0.2 {}
]
C {pump.sym} 250 -680 0 0 {name=x4 conduct="1.0/20000.0" val=4.5 embed=true}
[
v {xschem version=2.9.7 file_version=1.2}
G {type=subcircuit
format="@name @pinlist @symname"
template="name=x1 val=4.5 conduct=10.0"
generic_type="conduct=real val=real"}
V {}
S {}
E {}
L 4 -80 -10 70 -10 {}
L 4 -80 10 70 10 {}
L 4 -80 -10 -80 10 {}
L 4 70 -10 70 10 {}
L 4 70 0 90 0 {}
L 4 -100 0 -80 0 {}
B 5 87.5 -2.5 92.5 2.5 {name=USC sig_type=rreal verilog_type=wire dir=inout }
B 5 -102.5 -2.5 -97.5 2.5 {name=ING sig_type=std_logic verilog_type=wire dir=in }
T {@symname} -45 -6 0 0 0.3 0.3 {}
T {@name} 75 -22 0 0 0.2 0.2 {}
T {USC} 65 -4 0 1 0.2 0.2 {}
T {ING} -75 -4 0 0 0.2 0.2 {}
T {conduct=@conduct
val=@val} -65 -36 0 0 0.2 0.2 {}
]
C {lab_pin.sym} 150 -680 0 0 {name=l4 lab=ING embed=true}
[
v {xschem version=2.9.7 file_version=1.2}
G {type=label
format="*.alias @lab"
template="name=l1 sig_type=std_logic lab=xxx"}
V {}
S {}
E {}
B 5 -1.25 -1.25 1.25 1.25 {name=p dir=in}
T {@lab} -7.5 -8.125 0 1 0.33 0.33 {}
]
C {switch_rreal.sch} 660 -670 0 0 {name=x5 del="2 ns" embed=true}
[
v {xschem version=2.9.7 file_version=1.2}
G {type=subcircuit
format="@name @pinlist @symname"
template="name=x1 del=\\"2 ns\\""
generic_type="del=time"}
V {}
S {}
E {}
L 4 -110 -20 110 -20 {}
L 4 -110 20 110 20 {}
L 4 -110 -20 -110 20 {}
L 4 110 -20 110 20 {}
L 4 110 -10 150 -10 {}
L 4 -150 -10 -110 -10 {}
L 4 -150 10 -110 10 {}
L 7 -140 7.5 -137.5 10 {}
L 7 -140 12.5 -137.5 10 {}
L 7 -142.5 -10 -140 -12.5 {}
L 7 -142.5 -10 -140 -7.5 {}
L 7 -140 -12.5 -137.5 -10 {}
L 7 -140 -7.5 -137.5 -10 {}
L 7 140 -12.5 142.5 -10 {}
L 7 140 -7.5 142.5 -10 {}
L 7 137.5 -10 140 -12.5 {}
L 7 137.5 -10 140 -7.5 {}
B 5 -152.5 7.5 -147.5 12.5 {name=ENAB dir=in }
B 5 147.5 -12.5 152.5 -7.5 {name=B dir=inout sig_type=rreal}
B 5 -152.5 -12.5 -147.5 -7.5 {name=A dir=inout sig_type=rreal}
T {@symname} -49.5 -6 0 0 0.3 0.3 {}
T {@name} 65 -32 0 0 0.2 0.2 {}
T {$ENAB} -146.25 -6.25 0 0 0.2 0.2 {}
T {$A} -146.25 -26.25 0 0 0.2 0.2 {}
T {$B} 146.25 -26.25 0 1 0.2 0.2 {}
]
C {lab_pin.sym} 510 -660 0 0 {name=l5 lab=SW embed=true}
C {real_capa.sym} 450 -540 0 0 {name=x3 cap=30.0 embed=true}
[
v {xschem version=2.9.7 file_version=1.2}
G {type=subcircuit
format="@name @pinlist @symname"
template="name=x1 cap=10.0"
generic_type="cap=real"
}
V {}
S {}
E {}
L 4 0 5 0 30 {}
L 4 0 -30 0 -5 {}
L 4 -10 -5 10 -5 {}
L 4 -10 5 10 5 {}
L 4 2.5 -22.5 7.5 -22.5 {}
L 4 5 -25 5 -20 {}
L 4 -5 30 5 30 {}
L 4 0 35 5 30 {}
L 4 -5 30 0 35 {}
B 5 -2.5 -32.5 2.5 -27.5 {name=USC sig_type=rreal verilog_type=wire dir=inout }
T {@symname} 14.5 -6 0 0 0.3 0.3 {}
T {@name} 15 -17 0 0 0.2 0.2 {}
T {USC} -5 -24 0 1 0.2 0.2 {}
T {@cap pF} 14.5 14 0 0 0.3 0.3 {}
]
C {real_capa.sym} 830 -540 0 0 {name=x1 cap=100.0 embed=true}
C {switch_rreal.sch} 1050 -670 0 0 {name=x2 del="2 ns" embed=true}
C {lab_pin.sym} 900 -660 0 0 {name=l2 lab=SW1 embed=true}
C {lab_pin.sym} 1240 -680 0 1 {name=l3 lab=SP sig_type=rrreal embed=true}
C {real_capa.sym} 1230 -540 0 0 {name=x6 cap=20.0 embed=true}
C {lab_wire.sym} 860 -680 0 1 {name=l6 lab=VXS sig_type=rrreal
embed=true}
[
v {xschem version=2.9.7 file_version=1.2}
G {type=label
format="*.alias @lab"
template="name=l1 sig_type=std_logic lab=xxx"}
V {}
S {}
E {}
B 5 -1.25 -1.25 1.25 1.25 {name=p dir=in}
T {@lab} -2.5 -1.25 2 0 0.27 0.27 {}
]
C {pump.sym} 250 -800 0 0 {name=x7 conduct="1.0/40000.0" val=3.0 embed=true}
C {lab_pin.sym} 150 -800 0 0 {name=l7 lab=ING1 embed=true}
C {switch_rreal.sym} 630 -790 0 0 {name=x8 del="2 ns" embed=true}
[
v {xschem version=2.9.7 file_version=1.2}
G {type=subcircuit
format="@name @pinlist @symname"
template="name=x1 del=\\"2 ns\\""
generic_type="del=time"}
V {}
S {}
E {}
L 4 -130 -20 130 -20 {}
L 4 -130 20 130 20 {}
L 4 -130 -20 -130 20 {}
L 4 130 -20 130 20 {}
L 4 -150 10 -130 10 {}
L 4 130 -10 150 -10 {}
L 4 -150 -10 -130 -10 {}
B 5 -152.5 7.5 -147.5 12.5 {name=ENAB dir=in }
B 5 147.5 -12.5 152.5 -7.5 {name=B sig_type=rreal dir=inout }
B 5 -152.5 -12.5 -147.5 -7.5 {name=A sig_type=rreal dir=inout }
T {@symname} -49.5 -6 0 0 0.3 0.3 {}
T {@name} 135 -32 0 0 0.2 0.2 {}
T {ENAB} -125 6 0 0 0.2 0.2 {}
T {B} 125 -14 0 1 0.2 0.2 {}
T {A} -125 -14 0 0 0.2 0.2 {}
]
C {lab_pin.sym} 480 -780 0 0 {name=l0 lab=SW2 embed=true}
C {lab_wire.sym} 400 -800 0 1 {name=l8 lab=VX2 sig_type=rrreal
embed=true}
C {real_capa.sym} 350 -880 0 0 {name=x9 cap=40.0 embed=true}
C {package_not_shown.sym} 830 -340 0 0 {
library ieee, std;
use std.textio.all;
package rrreal is
type rreal is
record
value : real;
conduct : real;
cap : real;
end record;
type rreal_vector is array (natural range <>) of rreal;
function resolved_real( r: rreal_vector ) return rreal;
procedure print(s : in string);
subtype rrreal is resolved_real rreal;
type rrreal_vector is array (natural range <>) of rrreal;
CONSTANT RREAL_X : rreal := rreal'(value=> 0.0, cap=>0.0, conduct=>-1.0);
CONSTANT RREAL_Z : rreal := rreal'(value=> 0.0, cap=>0.0, conduct=>0.0);
CONSTANT RREAL_0 : rreal := rreal'(value=> 0.0, cap=>0.0, conduct=>10.0);
CONSTANT REAL_Z : real := 20.0;
CONSTANT REAL_X : real := 20.0;
procedure transition(
signal sig: INOUT rreal;
constant endval: IN real;
constant del: IN time
);
procedure glitch(
signal sig: INOUT rreal;
constant lowval: IN real;
constant endval: IN real;
constant del: IN time
);
end rrreal; -- end package declaration
package body rrreal is
procedure print(s : in string) is
variable outbuf: line;
begin
write(outbuf, s);
writeline(output, outbuf);
end procedure;
-- function resolved_real( r:rreal_vector) return rreal is
-- VARIABLE result : rreal := RREAL_Z;
-- begin
-- IF (r'LENGTH = 1) THEN RETURN r(r'LOW);
-- ELSE
-- FOR i IN r'RANGE LOOP
-- result.cap := result.cap + r(i).cap ;
-- IF r(i).value /=REAL_Z THEN
-- IF result.value /=REAL_Z THEN
-- result.value := REAL_X ;
-- ELSE
-- result.value := r(i).value ;
-- END IF;
-- END IF ;
-- END LOOP;
-- END IF;
-- RETURN result;
-- end resolved_real;
function resolved_real( r:rreal_vector) return rreal is
VARIABLE result : rreal := RREAL_Z;
variable vcapshare : real := 0.0;
begin
IF (r'LENGTH = 1) THEN RETURN r(r'LOW);
ELSE
FOR i IN r'RANGE LOOP
if r(i).conduct = -1.0 then
result := RREAL_X;
exit;
end if;
-- only process initialized (valid) data
if r(i).value > -30.0 and r(i).value < 30.0 then
if r(i).cap > -1.0e12 and r(i).cap < 1.0e12 then
if r(i).conduct > -1.0e12 and r(i).conduct < 1.0e12 then
vcapshare := vcapshare + r(i).value * r(i).cap;
result.value := result.value + r(i).value * r(i).conduct;
result.cap := result.cap + r(i).cap ;
if(r(i).conduct > 0.0 ) then
-- result.conduct := result.conduct + 1.0/r(i).conduct ;
result.conduct := result.conduct + r(i).conduct ;
end if;
end if;
end if;
end if;
END LOOP;
END IF;
if result.conduct /= 0.0 then
result.value := result.value / result.conduct ; -- conductance
-- result.value := result.value * result.conduct ; -- resistance
-- result.conduct := 1.0 / result.conduct;
elsif result.cap >0.0 then
result.value := vcapshare / result.cap;
else
result.value:=0.0;
end if;
RETURN result;
end resolved_real;
procedure transition(
signal sig: INOUT rreal;
constant endval: IN real;
constant del: IN time) is
variable step: real;
variable startval: real;
variable del2: time;
begin
del2 := del;
if del2 = 0 fs then
del2 := 1 ns;
end if;
startval := sig.value;
step := (endval-startval);
if abs(endval-startval) < 0.01 then --do not propagate events if endval very close to startval
return;
end if;
-- sig.value <= endval after del;
sig.value <= startval,
startval+0.25*step after del2*0.1,
startval+0.45*step after del2*0.2,
startval+0.60*step after del2*0.3,
startval+0.72*step after del2*0.4,
startval+0.80*step after del2*0.5,
startval+0.86*step after del2*0.6,
startval+0.90*step after del2*0.7,
startval+0.94*step after del2*0.8,
startval+0.97*step after del2*0.9,
endval after del2;
end transition;
procedure glitch(
signal sig: INOUT rreal;
constant lowval: IN real;
constant endval: IN real;
constant del: IN time) is
variable step: real;
variable step2: real;
variable startval: real;
variable del2 : time;
begin
del2 := del;
if del2 = 0 fs then
del2 := 1 ns;
end if;
startval := sig.value;
step := (lowval-startval);
step2 := (lowval-endval);
if abs(lowval-startval) < 0.01 then --do not propagate events if endval very close to startval
return;
end if;
sig.value <=
-- startval,
-- startval+0.25*step after del*0.05,
-- startval+0.45*step after del*0.1,
-- startval+0.60*step after del*0.15,
-- startval+0.72*step after del*0.2,
-- startval+0.80*step after del*0.25,
-- startval+0.86*step after del*0.3,
-- startval+0.90*step after del*0.35,
-- startval+0.94*step after del*0.4,
-- startval+0.97*step after del*0.45,
-- lowval after del*0.5,
-- lowval-0.25*step2 after del*0.55,
-- lowval-0.45*step2 after del*0.6,
-- lowval-0.60*step2 after del*0.65,
-- lowval-0.72*step2 after del*0.7,
-- lowval-0.80*step2 after del*0.75,
-- lowval-0.86*step2 after del*0.8,
-- lowval-0.90*step2 after del*0.85,
-- lowval-0.94*step2 after del*0.9,
-- lowval-0.97*step2 after del*0.95,
-- endval after del;
lowval,
lowval-0.25*step2 after del2*0.1,
lowval-0.45*step2 after del2*0.2,
lowval-0.60*step2 after del2*0.3,
lowval-0.72*step2 after del2*0.4,
lowval-0.80*step2 after del2*0.5,
lowval-0.86*step2 after del2*0.6,
lowval-0.90*step2 after del2*0.7,
lowval-0.94*step2 after del2*0.8,
lowval-0.97*step2 after del2*0.9,
endval after del2;
end glitch;
end rrreal; -- end package body
-- embed=true}
[
v {xschem version=2.9.7 file_version=1.2}
G {type=package
template="
-- THIS IS A TEMPLATE, REPLACE WITH ACTUAL CODE OR REMOVE INSTANCE!!
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package aaa is
type real_vector is array(natural range <>) of real;
constant dx : real := 0.001 ;
procedure assegna(
signal A : inout real;
signal A_OLD : in real;
A_VAL : in real
);
end aaa; -- end package declaration
package body aaa is
procedure assegna(
signal A : inout real;
signal A_OLD : in real;
A_VAL : in real ) is
constant tdelay: time := 0.01 ns;
begin
if (A /= A_VAL) then
A <= A_OLD+dx, A_VAL after tdelay;
end if;
end assegna;
end aaa; -- end package body
"}
V {}
S {}
E {}
L 4 0 -10 355 -10 {}
T {PACKAGE} 5 -25 0 0 0.3 0.3 {}
T {HIDDEN} 135 -5 0 0 0.3 0.3 {}
]
C {title.sym} 160 -40 0 0 {name=l9 author="Stefan Schippers" embed=true}
[
v {xschem version=2.9.7 file_version=1.2}
G {type=logo
template="name=l1 author=\\"Stefan Schippers\\""
verilog_ignore=true
vhdl_ignore=true
spice_ignore=true
tedax_ignore=true}
V {}
S {}
E {}
L 6 225 0 1020 0 {}
L 6 -160 0 -95 0 {}
T {@schname} 235 5 0 0 0.4 0.4 {}
T {@author} 235 -25 0 0 0.4 0.4 {}
T {@time_last_modified} 1020 -20 0 1 0.4 0.3 {}
T {SCHEM} 5 -25 0 0 1 1 {}
P 5 13 5 -30 -25 0 5 30 -15 30 -35 10 -55 30 -75 30 -45 0 -75 -30 -55 -30 -35 -10 -15 -30 5 -30 {fill=true}
]
C {arch_declarations.sym} 830 -280 0 0 {
signal V_VX, V_VX2, V_VXS, V_SP: real;
-- embed=true}
[
v {xschem version=2.9.7 file_version=1.2}
G {type=arch_declarations
template="
signal AAA: std_logic;
"}
V {}
S {}
E {}
L 4 -0 -10 355 -10 {}
T {ARCHITECTURE DECLARATIONS} 5 -25 0 0 0.3 0.3 {}
T {HIDDEN} 45 5 0 0 0.2 0.2 {}
]
C {lab_wire.sym} 430 -680 0 1 {name=l1 lab=VX sig_type=rrreal embed=true}

View File

@ -1,44 +0,0 @@
* LM324 OPERATIONAL AMPLIFIER "MACROMODEL" SUBCIRCUIT
* CREATED USING PARTS RELEASE 4.01 ON 09/08/89 AT 10:54
* (REV N/A) SUPPLY VOLTAGE: 5V
* CONNECTIONS: NON-INVERTING INPUT
* | INVERTING INPUT
* | | POSITIVE POWER SUPPLY
* | | | NEGATIVE POWER SUPPLY
* | | | | OUTPUT
* | | | | |
.SUBCKT LM324 1 2 3 4 5
*
C1 11 12 5.544E-12
C2 6 7 20.00E-12
DC 5 53 DX
DE 54 5 DX
DLP 90 91 DX
DLN 92 90 DX
DP 4 3 DX
EGND 99 0 POLY(2) (3,0) (4,0) 0 .5 .5
FB 7 99 POLY(5) VB VC VE VLP VLN 0 15.91E6 -20E6 20E6 20E6 -20E6
GA 6 0 11 12 125.7E-6
GCM 0 6 10 99 7.067E-9
IEE 3 10 DC 10.04E-6
HLIM 90 0 VLIM 1K
Q1 11 2 13 QX
Q2 12 1 14 QX
R2 6 9 100.0E3
RC1 4 11 7.957E3
RC2 4 12 7.957E3
RE1 13 10 2.773E3
RE2 14 10 2.773E3
REE 10 99 19.92E6
RO1 8 5 50
RO2 7 99 50
RP 3 4 30.31E3
VB 9 0 DC 0
VC 3 53 DC 2.100
VE 54 4 DC .6
VLIM 7 8 DC 0
VLP 91 0 DC 40
VLN 0 92 DC 40
.MODEL DX D(IS=800.0E-18)
.MODEL QX PNP(IS=800.0E-18 BF=250)
.ENDS

View File

@ -1,61 +0,0 @@
** node order
* 1: gnd
* 2: trig
* 3: out
* 4: reset#
* 5: ctrl
* 6: thres
* 7: dis
* 8: vcc
.SUBCKT ne555 34 32 30 19 23 33 1 21
* G TR O R F TH D V
Q4 25 2 3 QP
Q5 34 6 3 QP
Q6 6 6 8 QP
R1 9 21 4.7K
R2 3 21 830
R3 8 21 4.7K
Q7 2 33 5 QN
Q8 2 5 17 QN
Q9 6 4 17 QN
Q10 6 23 4 QN
Q11 12 20 10 QP
R4 10 21 1K
Q12 22 11 12 QP
Q13 14 13 12 QP
Q14 34 32 11 QP
Q15 14 18 13 QP
R5 14 34 100K
R6 22 34 100K
R7 17 34 10K
Q16 1 15 34 QN
Q17 15 19 31 QP
R8 18 23 5K
R9 18 34 5K
R10 21 23 5K
Q18 27 20 21 QP
Q19 20 20 21 QP
R11 20 31 5K
D1 31 24 DA
Q20 24 25 34 QN
Q21 25 22 34 QN
Q22 27 24 34 QN
R12 25 27 4.7K
R13 21 29 6.8K
Q23 21 29 28 QN
Q24 29 27 16 QN
Q25 30 26 34 QN
Q26 21 28 30 QN
D2 30 29 DA
R14 16 15 100
R15 16 26 220
R16 16 34 4.7K
R17 28 30 3.9K
Q3 2 2 9 QP
.MODEL DA D (RS=40 IS=1.0E-14 CJO=1PF)
.MODEL QP PNP (level=1 BF=20 BR=0.02 RC=4 RB=25 IS=1.0E-14 VA=50 NE=2)
+ CJE=12.4P VJE=1.1 MJE=.5 CJC=4.02P VJC=.3 MJC=.3 TF=229P TR=159N)
.MODEL QN NPN (level=1 IS=5.07F NF=1 BF=100 VAF=161 IKF=30M ISE=3.9P NE=2
+ BR=4 NR=1 VAR=16 IKR=45M RE=1.03 RB=4.12 RC=.412 XTB=1.5
+ CJE=12.4P VJE=1.1 MJE=.5 CJC=4.02P VJC=.3 MJC=.3 TF=229P TR=959P)
.ENDS

View File

@ -1,73 +0,0 @@
* hdif = 0.5e-6
.MODEL CMOSN NMOS (
+LEVEL = 49 acm = 3
+VERSION = 3.1 TNOM = 27 TOX = 7.7E-9
+XJ = 1E-7 NCH = 2.3579E17 VTH0 = 0.5048265
+K1 = 0.5542796 K2 = 0.0155863 K3 = 2.3475646
+K3B = -3.3142916 W0 = 4.145888E-5 NLX = 1.430868E-7
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = -0.0150839 DVT1 = 1.51022E-3 DVT2 = 0.170688
+U0 = 415.8570638 UA = 5.057324E-11 UB = 1.496793E-18
+UC = 2.986268E-11 VSAT = 1.237033E5 A0 = 0.9098788
+AGS = 0.2120181 B0 = 1.683612E-6 B1 = 5E-6
+KETA = -4.011887E-4 A1 = 0 A2 = 1
+RDSW = 1.156967E3 PRWG = -8.468558E-3 PRWB = -7.678669E-3
+WR = 1 WINT = 5.621821E-8 LINT = 1.606205E-8
+XL = -2E-8 XW = 0 DWG = -6.450939E-9
+DWB = 6.530228E-9 VOFF = -0.1259348 NFACTOR = 0.3344887
+CIT = 0 CDSC = 1.527511E-3 CDSCD = 0
+CDSCB = 0 ETA0 = 1.21138E-3 ETAB = -1.520242E-4
+DSUB = 0.1259886 PCLM = 0.8254768 PDIBLC1 = 0.4211084
+PDIBLC2 = 6.081164E-3 PDIBLCB = -5.865856E-6 DROUT = 0.7022263
+PSCBE1 = 7.238634E9 PSCBE2 = 5E-10 PVAG = 0.6261655
+DELTA = 0.01 MOBMOD = 1 PRT = 0
+UTE = -1.5 KT1 = -0.11 KT1L = 0
+KT2 = 0.022 UA1 = 4.31E-9 UB1 = -7.61E-18
+UC1 = -5.6E-11 AT = 3.3E4 WL = 0
+WLN = 1 WW = -1.22182E-15 WWN = 1.137
+WWL = 0 LL = 0 LLN = 1
+LW = 0 LWN = 1 LWL = 0
+CAPMOD = 2 XPART = 0.4 CGDO = 1.96E-10
+CGSO = 1.96E-10 CGBO = 0 CJ = 8.829973E-4
+PB = 0.7946332 MJ = 0.3539285 CJSW = 2.992362E-10
+PBSW = 0.9890846 MJSW = 0.1871372 PVTH0 = -0.0148617
+PRDSW = -114.7860236 PK2 = -5.151187E-3 WKETA = 5.687313E-3
+LKETA = -0.018518 )
*
* hdif = 0.5e-6
.MODEL CMOSP PMOS (
+LEVEL = 49 acm = 3
+VERSION = 3.1 TNOM = 27 TOX = 7.7E-9
+XJ = 1E-7 NCH = 8.52E16 VTH0 = -0.6897992
+K1 = 0.4134289 K2 = -5.342989E-3 K3 = 24.8361788
+K3B = -1.4390847 W0 = 2.467689E-6 NLX = 3.096223E-7
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 1.3209807 DVT1 = 0.4695965 DVT2 = -8.790762E-4
+U0 = 150.6275733 UA = 2.016943E-10 UB = 1.714919E-18
+UC = -1.36948E-11 VSAT = 9.559222E4 A0 = 0.9871247
+AGS = 0.3541967 B0 = 3.188091E-6 B1 = 5E-6
+KETA = -0.0169877 A1 = 0 A2 = 1
+RDSW = 2.443009E3 PRWG = 0.0260616 PRWB = 0.141561
+WR = 1 WINT = 5.038936E-8 LINT = 1.650588E-9
+XL = -2E-8 XW = 0 DWG = -1.535456E-8
+DWB = 1.256904E-8 VOFF = -0.15 NFACTOR = 1.5460516
+CIT = 0 CDSC = 1.413317E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 0.3751392 ETAB = 2.343374E-3
+DSUB = 0.8877574 PCLM = 5.8638076 PDIBLC1 = 1.05224E-3
+PDIBLC2 = 3.481753E-5 PDIBLCB = 2.37525E-3 DROUT = 0.0277454
+PSCBE1 = 3.013379E10 PSCBE2 = 3.608179E-8 PVAG = 3.9564294
+DELTA = 0.01 MOBMOD = 1 PRT = 0
+UTE = -1.5 KT1 = -0.11 KT1L = 0
+KT2 = 0.022 UA1 = 4.31E-9 UB1 = -7.61E-18
+UC1 = -5.6E-11 AT = 3.3E4 WL = 0
+WLN = 1 WW = -5.22182E-16 WWN = 1.125
+WWL = 0 LL = 0 LLN = 1
+LW = 0 LWN = 1 LWL = 0
+CAPMOD = 2 XPART = 0.4 CGDO = 2.307E-10
+CGSO = 2.307E-10 CGBO = 0 CJ = 1.397645E-3
+PB = 0.99 MJ = 0.5574537 CJSW = 3.665392E-10
+PBSW = 0.99 MJSW = 0.3399328 PVTH0 = 0.0114364
+PRDSW = 52.7951169 PK2 = 9.714153E-4 WKETA = 0.0109418
+LKETA = 7.702974E-3 )

View File

@ -1,50 +0,0 @@
*2N4401
*Si 310mW 40V 600mA 250MHz pkg:TO-92 1,2,3
.MODEL Q2N4401 NPN(IS=9.09E-15 BF=300 VAF=113 IKF=0.36 ISE=1.06E-11
+ NE=2 BR=4 VAR=24 IKR=0.54 RB=1.27 RE=0.319 RC=0.127 CJE=2.34E-11 TF=5.12E-10
+ CJC=1.02E-11 TR=1.51E-7 XTB=1.5 )
******
*SRC=2N4403;2N4403;BJTs PNP; Si; 40.0V 0.60A 200MHz Central Semi Central Semi
.MODEL Q2N4403 PNP (
+ IS=16.832E-15
+ BF=255.25
+ VAF=100
+ IKF=.77357
+ ISE=16.832E-15
+ NE=2
+ BR=14.207
+ VAR=100
+ IKR=53.456E-3
+ ISC=1.0152E-12
+ NC=1.7291
+ NK=.81917
+ RB=3.9257
+ RC=.51317
+ CJE=28.204E-12
+ VJE=.94511
+ MJE=.4306
+ CJC=25.033E-12
+ VJC=.51188
+ MJC=.4892
+ TF=550.52E-12
+ XTF=3.9312
+ VTF=4.0632
+ ITF=40.353E-3
+ TR=10.000E-9)
******
*SRC=1N914;1N914;Diodes;Si;100V 150mA 4.0ns Central Semi Central Semi
.MODEL D1N914 D ( IS=6.2229E-9
+ N=1.9224
+ RS=.33636
+ IKF=42.843E-3
+ CJO=764.38E-15
+ M=.1001
+ VJ=9.9900
+ ISR=11.526E-9
+ NR=4.9950
+ BV=100.14
+ IBV=.25951
+ TT=2.8854E-9 )
******

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@ -1,7 +0,0 @@
.MODEL Q2N2222A NPN IS =3.0611E-14 NF =1.00124 BF =220 IKF=0.52
+ VAF=104 ISE=7.5E-15 NE =1.41 NR =1.005 BR =4 IKR=0.24
+ VAR=28 ISC=1.06525E-11 NC =1.3728 RB =0.13 RE =0.22
+ RC =0.12 CJC=9.12E-12 MJC=0.3508 VJC=0.4089
+ CJE=27.01E-12 TF =0.325E-9 TR =100E-9
+ vce_max=45 vbe_max=6

View File

@ -1,759 +0,0 @@
.MODEL bd139_2 npn
+IS=1e-09 BF=222.664 NF=0.85 VAF=36.4079
+IKF=0.166126 ISE=5.03418e-09 NE=1.45313 BR=1.35467
+NR=1.33751 VAR=142.931 IKR=1.66126 ISC=5.02557e-09
+NC=3.10227 RB=26.9143 IRB=0.1 RBM=0.1
+RE=0.000472454 RC=1.04109 XTB=0.727762 XTI=1.04311
+EG=1.05 CJE=1e-11 VJE=0.75 MJE=0.33
+TF=1e-09 XTF=1 VTF=10 ITF=0.01
+CJC=1e-11 VJC=0.75 MJC=0.33 XCJC=0.9
+FC=0.5 CJS=0 VJS=0.75 MJS=0.5
+TR=1e-07 PTF=0 KF=0 AF=1
.MODEL BD139 NPN (
+IS=2.3985E-13 Vceo=80 Icrating=1500m
+BF=244.9 NF=1.0 BR=78.11 NR=1.007 ISE=1.0471E-14
+NE=1.2 ISC=1.9314E-11 NC=1.45 VAF=98.5 VAR=7.46
+IKF=1.1863 IKR=0.1445 RB=2.14 RBM=0.001 IRB=0.031
+RE=0.0832 RC=0.01 CJE=2.92702E-10 VJE=0.67412
+MJE=0.3300 FC=0.5 CJC=4.8831E-11 VJC=0.5258
+MJC=0.3928 XCJC=0.5287 XTB=1.1398 EG=1.2105 XTI=3.0)
.MODEL BD140 PNP(IS=1e-09 BF=650.842 NF=0.85 VAF=10
+IKF=0.0950125 ISE=1e-08 NE=1.54571 BR=56.177
+NR=1.5 VAR=2.11267 IKR=0.950125 ISC=1e-08
+NC=3.58527 RB=41.7566 IRB=0.1 RBM=0.108893
+RE=0.000347052 RC=1.32566 XTB=19.5239 XTI=1
+EG=1.05 CJE=1e-11 VJE=0.75 MJE=0.33
+TF=1e-09 XTF=1 VTF=10 ITF=0.01
+CJC=1e-11 VJC=0.75 MJC=0.33 XCJC=0.9
+FC=0.5 CJS=0 VJS=0.75 MJS=0.5 TR=1e-07 PTF=0 KF=0 AF=10
+ VCEO=80 ICRATING=1A )
.MODEL Q2N2222A NPN IS =3.0611E-14 NF =1.00124 BF =220 IKF=0.52
+ VAF=104 ISE=7.5E-15 NE =1.41 NR =1.005 BR =4 IKR=0.24
+ VAR=28 ISC=1.06525E-11 NC =1.3728 RB =0.13 RE =0.22
+ RC =0.12 CJC=9.12E-12 MJC=0.3508 VJC=0.4089
+ CJE=27.01E-12 TF =0.325E-9 TR =100E-9
+ vce_max=45 vbe_max=6
.MODEL Q2N2222 NPN (
+ IS = 3.97589E-14 BF = 195.3412 NF = 1.0040078 VAF = 53.081 IKF = 0.976 ISE = 1.60241E-14
+ NE = 1.4791931 BR = 1.1107942 NR = 0.9928261 VAR = 11.3571702 IKR = 2.4993953 ISC = 1.88505E-12
+ NC = 1.1838278 RB = 56.5826472 IRB = 1.50459E-4 RBM = 5.2592283 RE = 0.0402974 RC = 0.4208
+ CJE = 2.56E-11 VJE = 0.682256 MJE = 0.3358856 TF = 3.3E-10 XTF = 6 VTF = 0.574
+ ITF = 0.32 PTF = 25.832 CJC = 1.40625E-11 VJC = 0.5417393 MJC = 0.4547893 XCJC = 1
+ TR = 3.2E-7 CJS = 0 VJS = .75 MJS = 0 XTB = 1.6486 EG = 1.11
+ XTI = 5.8315 KF = 0 AF = 1 FC = 0.83
+ vce_max=45 vbe_max=6 )
* 2n2222 p complementary
.MODEL Q2N2907P PNP(IS=650.6E-18 ISE=54.81E-15 ISC=0 XTI=3
+ BF=231.7 BR=3.563 IKF=1.079 IKR=0 XTB=1.5
+ VAF=115.7 VAR=35 VJE=0.65 VJC=0.65
+ RE=0.15 RC=0.715 RB=10
+ CJE=19.82E-12 CJC=14.76E-12 XCJC=0.75 FC=0.5
+ NF=1 NR=1 NE=1.829 NC=2 MJE=0.3357 MJC=0.5383
+ TF=603.7E-12 TR=111.3E-9 ITF=0.65 VTF=5 XTF=1.7
+ EG=1.11 KF=1E-9 AF=1
+ VCEO=45 ICRATING=100M
+ vce_max=45 vbe_max=6 )
.MODEL Q2N2907S PNP(IS=2.32E-13 ISE=6.69E-16 ISC=1.65E-13 XTI=3.00
+ BF=3.08E2 BR=2.18E1 IKF=8.42E-1 IKR=1.00 XTB=1.5
+ VAF=1.41E2 VAR=1.35E1 VJE=3.49E-1 VJC=3.00E-1
+ RE=1.00E-2 RC=8.46E-1 RB=4.02E1 RBM=1.00E-2 IRB=1.25E-2
+ CJE=2.66E-11 CJC=1.93E-11 XCJC=1.00 FC=5.00E-1
+ NF=1.04 NR=1.12 NE=1.09 NC=1.13 MJE=4.60E-1 MJC=4.65E-1
+ TF=4.95E-10 TR=0 PTF=0 ITF=3.36E-1 VTF=6.54 XTF=1.87E1
+ EG=1.11 KF=1E-9 AF=1
+ VCEO=40 ICRATING=500M
+ vce_max=45 vbe_max=6 )
*MM3725 MCE 5/13/95
*Si 1W 40V 500mA 307MHz pkg:TO-39 3,2,1
.MODEL QMM3725 NPN (IS=50.7F NF=1 BF=162 VAF=113 IKF=.45 ISE=38.2P NE=2
+ BR=4 NR=1 VAR=24 IKR=.675 RE=.263 RB=1.05 RC=.105 XTB=1.5
+ CJE=62.2P VJE=1.1 MJE=.5 CJC=14.6P VJC=.3 MJC=.3 TF=518P TR=45.9N)
*MPS651 MCE 5/12/95
*Si 625mW 60V 2A 110MHz pkg:TO-92 1,2,3
.MODEL QMPS651 NPN (IS=72.1F NF=1 BF=260 VAF=139 IKF=2.5 ISE=67.1P NE=2
+ BR=4 NR=1 VAR=20 IKR=3.75 RE=28.2M RB=.113 RC=11.3M XTB=1.5
+ CJE=212P VJE=1.1 MJE=.5 CJC=68.6P VJC=.3 MJC=.3 TF=1.44N TR=1U)
*FCX649 ZETEX Spice model Last revision 17/7/90 Medium Power
*ZTX Si 1.5W 25V 2A 240MHz pkg:SOT-89 2,1,3
.MODEL QFCX649 NPN(IS=3E-13 BF=225 VAF=80 IKF=2.8 ISE=1.1E-13 NE=1.37
+ BR=110 NR=0.972 VAR=28 IKR=0.8 ISC=6.5E-13 NC=1.372 RB=0.3 RE=0.063
+ RC=0.07 CJE=3.25E-10 TF=1E-9 CJC=7E-11 TR=1E-8 )
*MPSW01A MCE 5/12/95
*Si 1W 40V 1A 210MHz pkg:TO-92 1,2,3
.MODEL QMPSW01A NPN (IS=18.1F NF=1 BF=273 VAF=113 IKF=.6 ISE=15.7P NE=2
+ BR=4 NR=1 VAR=20 IKR=.9 RE=96.5M RB=.386 RC=38.6M XTB=1.5
+ CJE=78.7P VJE=1.1 MJE=.5 CJC=17.3P VJC=.3 MJC=.3 TF=757P TR=526N)
*BC546 ZETEX Spice model Last revision 4/90 General Purpose
*ZTX Si 500mW 65V 200mA 300MHz pkg:TO-92 1,2,3
.MODEL BC546 NPN(IS=1.8E-14 BF=400 NF=0.9955 VAF=80 IKF=0.14 ISE=5E-14
+ NE=1.46 BR=35.5 NR=1.005 VAR=12.5 IKR=0.03 ISC=1.72E-13 NC=1.27 RB=0.56
+ RE=0.6 RC=0.25 CJE=1.3E-11 TF=6.4E-10 CJC=4E-12 VJC=0.54 TR=5.072E-8
+ vce_max=65 vbe_max=6 )
.MODEL BC556 PNP(
+ IS=2.059E-14
+ NF=1.003
+ ISE=2.971E-15
+ NE=1.316
+ BF=227.3
+ IKF=0.08719
+ VAF=37.2
+ NR=1.007
+ ISC=1.339E-14
+ NC=1.15
+ BR=7.69
+ IKR=0.07646
+ VAR=11.42
+ RB=1
+ IRB=1E-06
+ RBM=1
+ RE=0.688
+ RC=0.6437
+ XTB=0
+ EG=1.11
+ XTI=3
+ CJE=1.4E-11
+ VJE=0.5912
+ MJE=0.3572
+ TF=7.046E-10
+ XTF=4.217
+ VTF=5.367
+ ITF=0.1947
+ PTF=0
+ CJC=1.113E-11
+ VJC=0.1
+ MJC=0.3414
+ XCJC=0.6288
+ TR=1E-32
+ CJS=0
+ VJS=0.75
+ MJS=0.333
+ FC=0.7947
+ vce_max=65 vbe_max=6 )
*
* NXP Semiconductors
*
* Medium power NPN transistor
* IC = 1 A
* VCEO = 20 V
* hFE = 85 - 375 @ 2V/500mA
*
*
*
*
* Package pinning does not match Spice model pinning.
* Package: SOT 223
*
* Package Pin 1: Base
* Package Pin 2: Collector
* Package Pin 3: Emitter
* Package Pin 4: Collector
*
* Extraction date (week/year): 13/2008
* Simulator: Spice 3
*
**********************************************************
*#
.SUBCKT BCP68 1 2 3
*
Q1 1 2 3 BCP68
D1 2 1 DIODE
*
*The diode does not reflect a
*physical device but improves
*only modeling in the reverse
*mode of operation.
*
.MODEL BCP68 NPN
+ IS = 2.312E-013
+ NF = 0.988
+ ISE = 8.851E-014
+ NE = 2.191
+ BF = 273
+ IKF = 5.5
+ VAF = 50
+ NR = 0.9885
+ ISC = 6.808E-014
+ NC = 3
+ BR = 155.6
+ IKR = 4
+ VAR = 17
+ RB = 15
+ IRB = 2E-006
+ RBM = 0.65
+ RE = 0.073
+ RC = 0.073
+ XTB = 0
+ EG = 1.11
+ XTI = 3
+ CJE = 2.678E-010
+ VJE = 0.732
+ MJE = 0.3484
+ TF = 5.8E-010
+ XTF = 1.5
+ VTF = 2.5
+ ITF = 1
+ PTF = 0
+ CJC = 3.406E-011
+ VJC = 2
+ MJC = 0.3142
+ XCJC = 1
+ TR = 6.5E-009
+ CJS = 0
+ VJS = 0.75
+ MJS = 0.333
+ FC = 0.95
.MODEL DIODE D
+ IS = 2.702E-015
+ N = 1.2
+ BV = 1000
+ IBV = 0.001
+ RS = 0.1
+ CJO = 0
+ VJ = 1
+ M = 0.5
+ FC = 0
+ TT = 0
+ EG = 1.11
+ XTI = 3
.ENDS
.model D1N4007 D(IS=7.02767n RS=0.0341512 N=1.80803 EG=1.05743 XTI=5 BV=1000 IBV=5e-08 CJO=1e-11 VJ=0.7 M=0.5 FC=0.5 TT=1e-07 )
.MODEL D1N4148 D
+ IS = 4.352E-9
+ N = 1.906
+ BV = 110
+ IBV = 0.0001
+ RS = 0.6458
+ CJO = 7.048E-13
+ VJ = 0.869
+ M = 0.03
+ FC = 0.5
+ TT = 3.48E-9
.MODEL D1n5400 d
+IS=2.61339e-12 RS=0.0110501 N=1.20576 EG=0.6
+XTI=3.1271 BV=50 IBV=1e-05 CJO=1e-11
+VJ=0.7 M=0.5 FC=0.5 TT=1e-09
+KF=0 AF=1
* Model generated on October 12, 2003
* Model format: PSpice
*1N758
*Ref: Motorola
*10V 500mW Si Zener pkg:DIODE0.4 1,2
.MODEL D1N758 D(IS=1E-11 RS=8.483 N=1.27 TT=5E-8 CJO=2.334E-10 VJ=0.75
+ M=0.33 BV=9.83 IBV=0.01 )
*1N4744
*Ref: Motorola
*15V 1W Si Zener pkg:DIODE0.4 1,2
.MODEL D1N4744 D(IS=5.32E-14 RS=6.47 TT=5.01E-8 CJO=7.83E-11 M=0.33
+ BV=14.89 IBV=0.017 )
*1N755
*Ref: Motorola
*7.5V 500mW Si Zener pkg:DIODE0.4 1,2
.MODEL D1N755 D(IS=1E-11 RS=3.359 N=1.27 TT=5E-8 CJO=2.959E-10 VJ=0.75
+ M=0.33 BV=7.433 IBV=0.01 )
** node order
* 1: gnd
* 2: trig
* 3: out
* 4: reset#
* 5: ctrl
* 6: thres
* 7: dis
* 8: vcc
.SUBCKT ne555 34 32 30 19 23 33 1 21
* G TR O R F TH D V
Q4 25 2 3 QP
Q5 34 6 3 QP
Q6 6 6 8 QP
R1 9 21 4.7K
R2 3 21 830
R3 8 21 4.7K
Q7 2 33 5 QN
Q8 2 5 17 QN
Q9 6 4 17 QN
Q10 6 23 4 QN
Q11 12 20 10 QP
R4 10 21 1K
Q12 22 11 12 QP
Q13 14 13 12 QP
Q14 34 32 11 QP
Q15 14 18 13 QP
R5 14 34 100K
R6 22 34 100K
R7 17 34 10K
Q16 1 15 34 QN
Q17 15 19 31 QP
R8 18 23 5K
R9 18 34 5K
R10 21 23 5K
Q18 27 20 21 QP
Q19 20 20 21 QP
R11 20 31 5K
D1 31 24 DA
Q20 24 25 34 QN
Q21 25 22 34 QN
Q22 27 24 34 QN
R12 25 27 4.7K
R13 21 29 6.8K
Q23 21 29 28 QN
Q24 29 27 16 QN
Q25 30 26 34 QN
Q26 21 28 30 QN
D2 30 29 DA
R14 16 15 100
R15 16 26 220
R16 16 34 4.7K
R17 28 30 3.9K
Q3 2 2 9 QP
.MODEL DA D RS=40 IS=1.0E-14 CJO=1PF
.MODEL QP PNP level=1 BF=20 BR=0.02 RC=4 RB=25 IS=1.0E-14 VA=50 NE=2
+ CJE=12.4P VJE=1.1 MJE=.5 CJC=4.02P VJC=.3 MJC=.3 TF=229P TR=159N
.MODEL QN NPN (level=1 IS=5.07F NF=1 BF=100 VAF=161 IKF=30M ISE=3.9P NE=2
+ BR=4 NR=1 VAR=16 IKR=45M RE=1.03 RB=4.12 RC=.412 XTB=1.5
+ CJE=12.4P VJE=1.1 MJE=.5 CJC=4.02P VJC=.3 MJC=.3 TF=229P TR=959P)
.ENDS
.SUBCKT BS250P 3 4 5
* D G S
M1 3 2 5 5 MBS250
RG 4 2 160
RL 3 5 1.2E8
C1 2 5 47E-12
C2 3 2 10E-12
D1 3 5 DBS250
*
.MODEL MBS250 PMOS VTO=-3.193 RS=2.041 RD=0.697 IS=1E-15 KP=0.277
+CBD=105E-12 PB=1 LAMBDA=1.2E-2
.MODEL DBS250 D IS=2E-13 RS=0.309
.ENDS BS250P
.SUBCKT BS170 3 4 5
* D G S
M1 3 2 5 5 N3306M
RG 4 2 270
RL 3 5 1.2E8
C1 2 5 28E-12
C2 3 2 3E-12
D1 5 3 N3306D
*
.MODEL N3306M NMOS VTO=1.824 RS=1.572 RD=1.436 IS=1E-15 KP=.1233
+CBD=35E-12 PB=1
.MODEL N3306D D IS=5E-12 RS=.768
.ENDS BS170
*
.SUBCKT irf540 1 2 3
M1 9 7 8 8 MM L=100u W=100u
* Default values used in MM:
* The voltage-dependent capacitances are
* not included. Other default values are:
* RS=0 RD=0 LD=0 CBD=0 CBS=0 CGBO=0
.MODEL MM NMOS LEVEL=1 IS=1e-32
+VTO=3.56362 LAMBDA=0.00291031 KP=25.0081
+CGSO=1.60584e-05 CGDO=4.25919e-07
RS 8 3 0.0317085
D1 3 1 MD
.MODEL MD D IS=1.02194e-10 RS=0.00968022 N=1.21527 BV=100
+IBV=0.00025 EG=1.2 XTI=3.03885 TT=1e-07
+CJO=1.81859e-09 VJ=1.1279 M=0.449161 FC=0.5
RDS 3 1 4e+06
RD 9 1 0.0135649
RG 2 7 5.11362
D2 4 5 MD1
* Default values used in MD1:
* RS=0 EG=1.11 XTI=3.0 TT=0
* BV=infinite IBV=1mA
.MODEL MD1 D IS=1e-32 N=50
+CJO=2.49697e-09 VJ=0.5 M=0.9 FC=1e-08
D3 0 5 MD2
* Default values used in MD2:
* EG=1.11 XTI=3.0 TT=0 CJO=0
* BV=infinite IBV=1mA
.MODEL MD2 D IS=1e-10 N=0.4 RS=3e-06
RL 5 10 1
FI2 7 9 VFI2 -1
VFI2 4 0 0
EV16 10 0 9 7 1
CAP 11 10 2.49697e-09
FI1 7 9 VFI1 -1
VFI1 11 6 0
RCAP 6 10 1
D4 0 6 MD3
* Default values used in MD3:
* EG=1.11 XTI=3.0 TT=0 CJO=0
* RS=0 BV=infinite IBV=1mA
.MODEL MD3 D IS=1e-10 N=0.4
.ENDS
.SUBCKT LM5134A VDD PILOT OUT IN INB VSS
E_E2 INB_INT 0 INB VSS 1
C_U3_C1 U3_N16789866 U3_N16789873 5p
X_U3_U5 VDD U3_N16789873 U3_N16790218 0 RVAR RREF=1
C_U3_C3 OUT U3_N16789866 1p
* E_U3_E1 U3_N16790231 OUT vol=' V(MGATE, 0) > 0.5? 5: -5'
E_U3_E1 U3_N16790231 OUT pwl(1) MGATE 0 0.49 -5 0.51 5
X_U3_U6 U3_N24836 VSS U3_N31827 0 RVAR RREF=1
R_U3_R1 U3_N16790231 U3_N16789866 20
M_U3_M2 U3_N24836 U3_N16789871 OUT OUT PMOS01
E_U3_E4 U3_N16790218 0 pwl(1) VDD_INT 0
+ 0 0, 4.5 0.9, 10 0.09, 12.6 0.08
X_U3_U10 VSS OUT d_d1
R_U3_R2 U3_N16789868 U3_N16789871 20
C_U3_C2 U3_N24836 U3_N16789871 5p
X_U3_U9 OUT VDD d_d1
C_U3_C5 OUT VDD 10p
C_U3_C6 OUT U3_N16789871 10p
C_U3_C4 VSS OUT 10p
M_U3_M1 U3_N16789873 U3_N16789866 OUT OUT NMOS01
E_U3_E3 U3_N31827 0 pwl(1) VDD_INT 0
+ 0 0, 4.5 0.26, 10 0.01, 12.6 0.01
E_U3_E2 OUT U3_N16789868 vol= 'V(MGATE, 0) > 0.5? -5: 5'
E_U4_ABM4 U4_N14683241 0 vol= 'V(U4_ON_INT) >=0.5?V(VDD_INT):0'
C_U4_C3 U4_N14683221 0 1n
V_U4_V6 U4_N155225261 0 80m
R_U4_R2 U4_N14683241 U4_N14683221 1
X_U4_U47 U4_N14683247 U4_N14683251 d_d1
E_U4_ABM5 U4_N14683301 0 vol= 'V(U4_ON_INT)<0.5? V(VDD_INT):0'
C_U4_C1 U4_N14683247 0 1n
X_U4_S1 U4_N14683159 0 U4_N14683247 0 PTON_TOFF_U4_S1
X_U4_U44 U4_ON_INT PGATE U4_N14683147 AND2_BASIC_GEN VDD=1
+ VSS=0 VTHRESH=500E-3
X_U4_U43 U4_N14683247 PGATE BUF_BASIC_GEN VDD=1 VSS=0
+ VTHRESH=0.5
R_U4_R3 U4_N14683301 U4_N14683281 1
X_U4_U7 N18232068 U4_N15541612 INV_BASIC_GEN VDD=1 VSS=0
+ VTHRESH=500E-3
G_U4_G1 U4_N14683251 U4_N14683247 pwl(1) U4_N14683221 0
+ 0 0, 4.5 140m, 10 500m, 12.6 600m
G_U4_G2 U4_N14683247 0 pwl(1) U4_N14683281 0
+ 0 0, 4.5 70m, 10 800m, 12.6 900m
X_U4_U8 MGATE U4_N15541600 INV_BASIC_GEN VDD=1 VSS=0
+ VTHRESH=500E-3
C_U4_C4 U4_N14683281 0 1n
X_U4_S2 U4_N14683147 0 U4_N14683251 U4_N14683247 PTON_TOFF_U4_S2
X_U4_U48 U4_N155225261 U4_N14683247 d_d1
X_U4_U45 U4_N15541600 U4_N15541612 U4_ON_INT AND2_BASIC_GEN
+ VDD=1 VSS=0 VTHRESH=500E-3
V_U4_V5 U4_N14683251 0 1V
X_U4_U46 PGATE U4_ON_INT U4_N14683159 NOR2_BASIC_GEN VDD=1
+ VSS=0 VTHRESH=500E-3
E_E1 IN_INT 0 IN VSS 1
E_E3 VDD_INT 0 VDD VSS 1
C_U2_C1 U2_N14683247 0 1n
X_U2_U46 MGATE U2_ON_INT U2_N14683159 NOR2_BASIC_GEN VDD=1
+ VSS=0 VTHRESH=500E-3
X_U2_U7 PGATE U2_N15532894 INV_BASIC_GEN VDD=1 VSS=0
+ VTHRESH=500E-3
G_U2_G1 U2_N14683251 U2_N14683247 pwl(1) U2_N14683221 0
+ 0 0, 4.5 58m, 10 140m, 12.6 230m
E_U2_ABM5 U2_N14683301 0 vol= 'V(U2_ON_INT) <0.5? V(VDD_INT):0'
X_U2_U43 U2_N14683247 MGATE BUF_BASIC_GEN VDD=1 VSS=0
+ VTHRESH=0.5
X_U2_U48 U2_N147032561 U2_N14683247 d_d1
V_U2_V6 U2_N147032561 0 80m
X_U2_S2 U2_N14683147 0 U2_N14683251 U2_N14683247 MTON_TOFF_U2_S2
E_U2_ABM4 U2_N14683241 0 vol='V(U2_ON_INT) >=0.5? V(VDD_INT):0 '
R_U2_R2 U2_N14683241 U2_N14683221 1
G_U2_G2 U2_N14683247 0 PWL(1) U2_N14683281 0
+ 0 0, 4.5 32m, 10 90m, 12.6 160m
V_U2_V5 U2_N14683251 0 1V
X_U2_U44 U2_ON_INT MGATE U2_N14683147 AND2_BASIC_GEN VDD=1
+ VSS=0 VTHRESH=500E-3
C_U2_C3 U2_N14683221 0 1n
X_U2_U45 N18232068 U2_N15532894 U2_ON_INT AND2_BASIC_GEN VDD=1
+ VSS=0 VTHRESH=500E-3
X_U2_S1 U2_N14683159 0 U2_N14683247 0 MTON_TOFF_U2_S1
R_U2_R3 U2_N14683301 U2_N14683281 1
C_U2_C4 U2_N14683281 0 1n
X_U2_U47 U2_N14683247 U2_N14683251 d_d1
X_U1_U6 INB_INT U1_VIH U1_VHYS U1_N15517298 COMPHYS_BASIC_GEN
+ VDD=1 VSS=0 VTHRESH=0.5
R_U1_R1 U1_N15521766 U1_VDD_UVLO 721.5
X_U1_U7 U1_N15517298 U1_INB_OUT INV_BASIC_GEN VDD=1 VSS=0
+ VTHRESH=500E-3
X_U1_U9 U1_IN_OUT U1_INB_OUT U1_VDD_UVLO N18232068 AND3_BASIC_GEN
+ VDD=1 VSS=0 VTHRESH=500E-3
C_U1_C1 U1_VDD_UVLO 0 1n
X_U1_U5 IN_INT U1_VIH U1_VHYS U1_IN_OUT COMPHYS_BASIC_GEN VDD=1
+ VSS=0 VTHRESH=0.5
X_U1_U8 VDD_INT U1_N15521824 U1_N15521760 U1_N15521766
+ COMPHYS_BASIC_GEN VDD=1 VSS=0 VTHRESH=0.5
V_U1_V1 U1_N15521824 0 3.6
E_U1_ABM3 U1_VHYS 0 vol= '0.34*V(VDD_INT)'
E_U1_ABM1 U1_VIH 0 vol='0.67*V(VDD_INT)'
V_U1_V2 U1_N15521760 0 0.36
X_U1_U35 U1_VDD_UVLO U1_N15521766 d_d1
M_U5_M2 U5_N16789896 U5_N23038 PILOT PILOT PMOS02
R_U5_R1 U5_N16790231 U5_N16789866 20
X_U5_U6 U5_N16789896 VSS U5_N16802670 0 RVAR RREF=1
M_U5_M1 U5_N08221 U5_N16789866 PILOT PILOT NMOS02
C_U5_C4 VSS PILOT 10p
C_U5_C2 U5_N16789896 U5_N23038 5p
R_U5_R2 U5_N16789868 U5_N23038 20
E_U5_E3 U5_N16802670 0 pwl(1) VDD_INT 0
+ 0 0, 4.5 2.8, 10 1.9, 12.6 1.6
X_U5_U5 VDD U5_N08221 U5_N26349 0 RVAR RREF=1
C_U5_C1 U5_N08221 U5_N16789866 5p
C_U5_C5 PILOT VDD 10p
E_U5_E4 U5_N26349 0 pwl(1) VDD_INT 0
+ 0 0, 4.5 9.5, 10 2.88, 12.6 2.8
X_U5_U9 PILOT VDD d_d1
C_U5_C3 PILOT U5_N16789866 10p
X_U5_U10 VSS PILOT d_d1
E_U5_E2 PILOT U5_N16789868 vol= ' V(PGATE, 0) > 0.5? -5: 5'
E_U5_E1 U5_N16790231 PILOT vol= ' V(PGATE, 0) > 0.5? 5: -5'
C_U5_C6 PILOT U5_N23038 10p
.ENDS LM5134A
*$
.SUBCKT PTON_TOFF_U4_S1 1 2 3 4
G_Switch 3 4 VCR PWL(1) 1 2 0.2 100e6 0.8 1m
RS_U4_S1 1 2 1G
.ENDS PTON_TOFF_U4_S1
*$
.SUBCKT PTON_TOFF_U4_S2 1 2 3 4
G_Switch 3 4 VCR PWL(1) 1 2 0.2 100e6 0.8 1m
RS_U4_S2 1 2 1G
.ENDS PTON_TOFF_U4_S2
*$
.SUBCKT MTON_TOFF_U2_S2 1 2 3 4
G_Switch 3 4 VCR PWL(1) 1 2 0.2 100e6 0.8 1m
RS_U2_S2 1 2 1G
.ENDS MTON_TOFF_U2_S2
*$
.SUBCKT MTON_TOFF_U2_S1 1 2 3 4
G_Switch 3 4 VCR PWL(1) 1 2 0.2 100e6 0.8 1m
RS_U2_S1 1 2 1G
.ENDS MTON_TOFF_U2_S1
*$
****************************** Basic Components **************************
.SUBCKT D_D1 1 2
D1 1 2 DD1
.MODEL DD1 D (IS=1e-15 Rs=0.001 N=0.1 TT=10p)
.ENDS D_D1
*$
.SUBCKT BUF_BASIC_GEN A Y VDD=1 VSS=0 VTHRESH=0.5
* E_ABMGATE YINT 0 vol='V(A) > VTHRESH? VDD:VSS'
E_ABMGATE YINT 0 pwl(1) A 0 'VTHRESH-0.01' VSS 'VTHRESH+0.01' VDD
RINT YINT Y 1
CINT Y 0 1n
.ENDS BUF_BASIC_GEN
*$
.MODEL NMOS01 NMOS (VTO = 2 KP = 1.005 LAMBDA = 0.001)
*$
.MODEL PMOS01 PMOS (VTO = -2 KP = 1.77 LAMBDA = 0.001)
*$
.MODEL NMOS02 NMOS (VTO = 2 KP = 0.1814 LAMBDA = 0.001)
*$
.MODEL PMOS02 PMOS (VTO = -2 KP = 0.2497 LAMBDA = 0.001)
*$
.SUBCKT COMPHYS_BASIC_GEN INP INM HYS OUT VDD=1 VSS=0 VTHRESH=0.5
EIN INP1 INM1 INP INM 1
* EHYS INP1 INP2 vol='V(1) > VTHRESH? -V(HYS):0'
EHYS INP1 INP2 pwl(1) 1 0 'VTHRESH-0.01' 0 'VTHRESH+0.01' '-V(HYS)'
EOUT OUT 0 vol='V(INP2)>V(INM1)? VDD : VSS'
R1 OUT 1 1
C1 1 0 5n
RINP1 INP1 0 1K
.ENDS COMPHYS_BASIC_GEN
*$
.SUBCKT AND2_BASIC_GEN A B Y VDD=1 VSS=0 VTHRESH=0.5
E_ABMGATE YINT 0 vol= 'V(A) > VTHRESH && V(B) > VTHRESH ? VDD:VSS'
RINT YINT Y 1
CINT Y 0 1n
.ENDS AND2_BASIC_GEN
*$
.SUBCKT NOR2_BASIC_GEN A B Y VDD=1 VSS=0 VTHRESH=0.5
E_ABMGATE YINT 0 vol= 'V(A) > VTHRESH || V(B) > VTHRESH ? VSS:VDD'
RINT YINT Y 1
CINT Y 0 1n
.ENDS NOR2_BASIC_GEN
*$
.SUBCKT AND3_BASIC_GEN A B C Y VDD=1 VSS=0 VTHRESH=0.5
E_ABMGATE YINT 0 vol= 'V(A) > VTHRESH && V(B) > VTHRESH && V(C) > VTHRESH ? VDD:VSS'
RINT YINT Y 1
CINT Y 0 1n
.ENDS AND3_BASIC_GEN
*$
.SUBCKT INV_BASIC_GEN A Y VDD=1 VSS=0 VTHRESH=0.5
* E_ABMGATE YINT 0 vol='V(A) > VTHRESH ? VSS : VDD'
E_ABMGATE YINT 0 pwl(1) A 0 'VTHRESH-0.01' VDD 'VTHRESH+0.01' VSS
RINT YINT Y 1
CINT Y 0 1n
.ENDS INV_BASIC_GEN
*$
.SUBCKT RVAR 101 102 201 202 RREF=1
* nodes : 101 102 : nodes between which variable resistance is placed
* 201 202 : nodes to whose voltage the resistance is proportional
* parameters : rref : reference value of the resistance
rin 201 202 1G $$ input resistance
r 301 0 rref
fcopy 0 301 vsense 1 $$ copy output current thru Z
eout 101 106 poly(2) 201 202 301 0 0 0 0 0 1 $$ multiply VoverZ with Vctrl
vsense 106 102 0 $$ sense iout
.ENDS RVAR
*$
*LM317 TI voltage regulator - pin order: In, Adj, Out
*TI adjustable voltage regulator pkg:TO-3
.SUBCKT LM317 1 2 3 **Changes my be required on this line**
J1 1 3 4 JN
Q2 5 5 6 QPL .1
Q3 5 8 9 QNL .2
Q4 8 5 7 QPL .1
Q5 81 8 3 QNL .2
Q6 3 81 10 QPL .2
Q7 12 81 13 QNL .2
Q8 10 5 11 QPL .2
Q9 14 12 10 QPL .2
Q10 16 5 17 QPL .2
Q11 16 14 15 QNL .2
Q12 3 20 16 QPL .2
Q13 1 19 20 QNL .2
Q14 19 5 18 QPL .2
Q15 3 21 19 QPL .2
Q16 21 22 16 QPL .2
Q17 21 3 24 QNL .2
Q18 22 22 16 QPL .2
Q19 22 3 241 QNL 2
Q20 3 25 16 QPL .2
Q21 25 26 3 QNL .2
Q22A 35 35 1 QPL 2
Q22B 16 35 1 QPL 2
Q23 35 16 30 QNL 2
Q24A 27 40 29 QNL .2
Q24B 27 40 28 QNL .2
Q25 1 31 41 QNL 5
Q26 1 41 32 QNL 50
D1 3 4 DZ
D2 33 1 DZ
D3 29 34 DZ
R1 1 6 310
R2 1 7 310
R3 1 11 190
R4 1 17 82
R5 1 18 5.6K
R6 4 8 100K
R7 8 81 130
R8 10 12 12.4K
R9 9 3 180
R10 13 3 4.1K
R11 14 3 5.8K
R12 15 3 72
R13 20 3 5.1K
R14 2 24 12K
R15 24 241 2.4K
R16 16 25 6.7K
R17 16 40 12K
R18 30 41 130
R19 16 31 370
R20 26 27 13K
R21 27 40 400
R22 3 41 160
R23 33 34 18K
R24 28 29 160
R25 28 32 3
R26 32 3 .1
C1 21 3 30PF
C2 21 2 30PF
C3 25 26 5PF
CBS1 5 3 2PF
CBS2 35 3 1PF
CBS3 22 3 1PF
.MODEL JN NJF(BETA=1E-4 VTO=-7)
.MODEL DZ D(BV=6.3)
.MODEL QNL NPN(EG=1.22 BF=80 RB=100 CCS=1.5PF TF=.3NS TR=6NS CJE=2PF
+ CJC=1PF VAF=100)
.MODEL QPL PNP(BF=40 RB=20 TF=.6NS TR=10NS CJE=1.5PF CJC=1PF VAF=50)
.ENDS
.SUBCKT xxxxLM317 1 3 2
* IN ADJ OUT
IADJ 1 4 50U
VREF 4 3 1.25
RC 1 14 0.742
DBK 14 13 D1
CBC 13 15 2.479N
RBC 15 5 247
QP 13 5 2 Q1
RB2 6 5 124
DSC 6 11 D1
ESC 11 2 POLY(2) (13,5) (6,5) 2.85
+ 0 0 0 -70.1M
DFB 6 12 D1
EFB 12 2 POLY(2) (13,5) (6,5) 3.92
+ -135M 0 1.21M -70.1M
RB1 7 6 1
EB 7 2 8 2 2.56
CPZ 10 2 0.796U
DPU 10 2 D1
RZ 8 10 0.104
RP 9 8 100
EP 9 2 4 2 103.6
RI 2 4 100MEG
.MODEL Q1 NPN (IS=30F BF=100
+ VAF=14.27 NF=1.604)
.MODEL D1 D (IS=30F N=1.604)
.ENDS
.SUBCKT LM337 8 1 19
*Connections Input Adj. Output
*LM337 negative voltage regulator
.MODEL QN NPN (BF=50 TF=1N CJC=1P)
.MODEL QPOUT PNP (BF=50 TF=1N RE=.2 CJC=1P)
.MODEL QP PNP CJC=1P TF=2N
.MODEL DN D
.MODEL D2 D BV=12 IBV=100U
R10 25 6 1K
Q3 8 17 16 QPOUT
Q4 8 25 17 QP
R18 19 17 250
R19 19 16 .3
G1 8 6 1 18 .1
C7 6 2 .04U
R24 2 8 100
I_ADJ 0 1 65U
R26 8 25 200K
Q5 25 4 19 QP
R27 16 4 200
R28 7 4 7K
D1 8 7 D2
D2 8 6 DN
V1 18 19 1.25
.ENDS

View File

@ -1,27 +0,0 @@
.MODEL D1N4148 D
+ IS = 4.352E-9
+ N = 1.906
+ BV = 110
+ IBV = 0.0001
+ RS = 0.6458
+ CJO = 7.048E-13
+ VJ = 0.869
+ M = 0.03
+ FC = 0.5
+ TT = 3.48E-9
.MODEL D1n5400 d
+IS=2.61339e-12 RS=0.0110501 N=1.20576 EG=0.6
+XTI=3.1271 BV=50 IBV=1e-05 CJO=1e-11
+VJ=0.7 M=0.5 FC=0.5 TT=1e-09
+KF=0 AF=1
.MODEL BD139 NPN (
+IS=2.3985E-13 Vceo=80 Icrating=1500m
+BF=244.9 NF=1.0 BR=78.11 NR=1.007 ISE=1.0471E-14
+NE=1.2 ISC=1.9314E-11 NC=1.45 VAF=98.5 VAR=7.46
+IKF=1.1863 IKR=0.1445 RB=2.14 RBM=0.001 IRB=0.031
+RE=0.0832 RC=0.01 CJE=2.92702E-10 VJE=0.67412
+MJE=0.3300 FC=0.5 CJC=4.8831E-11 VJC=0.5258
+MJC=0.3928 XCJC=0.5287 XTB=1.1398 EG=1.2105 XTI=3.0)

View File

@ -1,121 +0,0 @@
* Beta Version released on 2/22/06
* PTM 130nm NMOS
.model nmos nmos level = 54
+version = 4.5.0 binunit = 1 paramchk= 1 mobmod = 0
+capmod = 2 igcmod = 1 igbmod = 1 geomod = 1
+diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1
+permod = 1 acnqsmod= 0 trnqsmod= 0
+tnom = 27 toxe = 2.25e-9 toxp = 1.6e-9 toxm = 2.25e-9
+dtox = 0.65e-9 epsrox = 3.9 wint = 5e-009 lint = 10.5e-009
+ll = 0 wl = 0 lln = 1 wln = 1
+lw = 0 ww = 0 lwn = 1 wwn = 1
+lwl = 0 wwl = 0 xpart = 0 toxref = 2.25e-9
+xl = -60e-9
+vth0 = 0.3782 k1 = 0.4 k2 = 0.01 k3 = 0
+k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2
+dvt2 = -0.032 dvt0w = 0 dvt1w = 0 dvt2w = 0
+dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1.2e-010
+dvtp1 = 0.1 lpe0 = 0 lpeb = 0 xj = 3.92e-008
+ngate = 2e+020 ndep = 1.54e+018 nsd = 2e+020 phin = 0
+cdsc = 0.0002 cdscb = 0 cdscd = 0 cit = 0
+voff = -0.13 nfactor = 1.5 eta0 = 0.0092 etab = 0
+vfb = -0.55 u0 = 0.05928 ua = 6e-010 ub = 1.2e-018
+uc = 0 vsat = 100370 a0 = 1 ags = 1e-020
+a1 = 0 a2 = 1 b0 = 0 b1 = 0
+keta = 0.04 dwg = 0 dwb = 0 pclm = 0.06
+pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = -0.005 drout = 0.5
+pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 1e-007
+fprout = 0.2 pdits = 0.08 pditsd = 0.23 pditsl = 2.3e+006
+rsh = 5 rdsw = 200 rsw = 100 rdw = 100
+rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 0
+prwb = 6.8e-011 wr = 1 alpha0 = 0.074 alpha1 = 0.005
+beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002
+egidl = 0.8
+aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002
+nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004
+eigbinv = 1.1 nigbinv = 3 aigc = 0.012 bigc = 0.0028
+cigc = 0.002 aigsd = 0.012 bigsd = 0.0028 cigsd = 0.002
+nigc = 1 poxedge = 1 pigcd = 1 ntox = 1
+xrcrg1 = 12 xrcrg2 = 5
+cgso = 2.4e-010 cgdo = 2.4e-010 cgbo = 2.56e-011 cgdl = 2.653e-10
+cgsl = 2.653e-10 ckappas = 0.03 ckappad = 0.03 acde = 1
+moin = 15 noff = 0.9 voffcv = 0.02
+kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5
+ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0
+at = 33000
+fnoimod = 1 tnoimod = 0
+jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs = 1
+ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10 xjbvs = 1
+jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd = 1
+ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10 xjbvd = 1
+pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1
+cjsws = 5e-010 mjsws = 0.33 pbswgs = 1 cjswgs = 3e-010
+mjswgs = 0.33 pbd = 1 cjd = 0.0005 mjd = 0.5
+pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1
+cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001
+tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001
+xtis = 3 xtid = 3
+dmcg = 0e-006 dmci = 0e-006 dmdg = 0e-006 dmcgt = 0e-007
+dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008
+rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15
+rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1
* PTM 130nm PMOS
.model pmos pmos level = 54
+version = 4.5.0 binunit = 1 paramchk= 1 mobmod = 0
+capmod = 2 igcmod = 1 igbmod = 1 geomod = 1
+diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1
+permod = 1 acnqsmod= 0 trnqsmod= 0
+tnom = 27 toxe = 2.35e-009 toxp = 1.6e-009 toxm = 2.35e-009
+dtox = 0.75e-9 epsrox = 3.9 wint = 5e-009 lint = 10.5e-009
+ll = 0 wl = 0 lln = 1 wln = 1
+lw = 0 ww = 0 lwn = 1 wwn = 1
+lwl = 0 wwl = 0 xpart = 0 toxref = 2.35e-009
+xl = -60e-9
+vth0 = -0.321 k1 = 0.4 k2 = -0.01 k3 = 0
+k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2
+dvt2 = -0.032 dvt0w = 0 dvt1w = 0 dvt2w = 0
+dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1e-009
+dvtp1 = 0.05 lpe0 = 0 lpeb = 0 xj = 3.92e-008
+ngate = 2e+020 ndep = 1.14e+018 nsd = 2e+020 phin = 0
+cdsc = 0.000258 cdscb = 0 cdscd = 6.1e-008 cit = 0
+voff = -0.126 nfactor = 1.5 eta0 = 0.0092 etab = 0
+vfb = 0.55 u0 = 0.00835 ua = 2.0e-009 ub = 0.5e-018
+uc = -3e-011 vsat = 70000 a0 = 1.0 ags = 1e-020
+a1 = 0 a2 = 1 b0 = -1e-020 b1 = 0
+keta = -0.047 dwg = 0 dwb = 0 pclm = 0.12
+pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = 3.4e-008 drout = 0.56
+pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 9.58e-007
+fprout = 0.2 pdits = 0.08 pditsd = 0.23 pditsl = 2.3e+006
+rsh = 5 rdsw = 240 rsw = 120 rdw = 120
+rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 3.22e-008
+prwb = 6.8e-011 wr = 1 alpha0 = 0.074 alpha1 = 0.005
+beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002
+egidl = 0.8
+aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002
+nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004
+eigbinv = 1.1 nigbinv = 3 aigc = 0.69 bigc = 0.0012
+cigc = 0.0008 aigsd = 0.0087 bigsd = 0.0012 cigsd = 0.0008
+nigc = 1 poxedge = 1 pigcd = 1 ntox = 1
+xrcrg1 = 12 xrcrg2 = 5
+cgso = 2.4e-010 cgdo = 2.4e-010 cgbo = 2.56e-011 cgdl = 2.653e-10
+cgsl = 2.653e-10 ckappas = 0.03 ckappad = 0.03 acde = 1
+moin = 15 noff = 0.9 voffcv = 0.02
+kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5
+ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0
+at = 33000
+fnoimod = 1 tnoimod = 0
+jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs = 1
+ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10 xjbvs = 1
+jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd = 1
+ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10 xjbvd = 1
+pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1
+cjsws = 5e-010 mjsws = 0.33 pbswgs = 1 cjswgs = 3e-010
+mjswgs = 0.33 pbd = 1 cjd = 0.0005 mjd = 0.5
+pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1
+cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001
+tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001
+xtis = 3 xtid = 3
+dmcg = 0e-006 dmci = 0e-006 dmdg = 0e-006 dmcgt = 0e-007
+dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008
+rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15
+rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1

View File

@ -1,101 +0,0 @@
.SUBCKT M2N7002 20 10 30
Rg 10 1 1
M1 2 1 3 3 DMOS L=1u W=1u
.MODEL DMOS NMOS (VTO='2.1*(-0.0016*TEMPER+1.04)' KP=0.35 THETA=0.086 VMAX=2.2E5 LEVEL=3)
Cgs 1 3 60p
Rd 20 4 0.3 TC=0.0075
Dds 3 4 DDS
.MODEL DDS D(BV='60*(0.00072*TEMPER+0.982)' M=0.36 CJO=23p VJ=0.8)
Dbody 3 20 DBODY
.MODEL DBODY D(IS=1.4E-13 N=1 RS=40m TT=100n)
Ra 4 2 0.4 TC=0.0075
Rs 3 5 10m
Ls 5 30 .5n
M2 1 8 6 6 INTER
E2 8 6 4 1 2
.MODEL INTER NMOS(VTO=0 KP=10 LEVEL=1)
Cgdmax 7 4 85p
Rcgd 7 4 10meg
Dgd 6 4 DGD
Rdgd 4 6 10meg
.MODEL DGD D(M=0.53 CJO=85p VJ=0.12)
M3 7 9 1 1 INTER
E3 9 1 4 1 -2
.ENDS M2N7002
* PINOUT ORDER +IN -IN +V -V OUT
* PINOUT ORDER 1 2 3 4 5
.SUBCKT LM358 1 2 3 4 5
R44 4 6 4E4
I1 4 7 0.5E-6
Q1 4 8 9 QPI
Q2 4 2 10 QPA
Q3 9 9 11 QPI
Q4 10 10 11 QPI
Q5 12 13 4 QNQ
Q6 13 13 4 QNQ
Q7 4 12 14 QPQ
Q8 3 14 6 QNQ
Q9 15 6 4 QNQ
Q10 3 15 16 QNQ
Q11 3 16 17 QNQ
R67 17 16 4E4
R68 5 17 18
Q12 4 15 5 QPQ
Q13 15 17 5 QNQ
I2 18 3 120E-9
I3 19 3 60E-9
I4 20 3 1E-6
Q14 11 18 3 QPQ
Q15 14 19 3 QPQ
Q16 5 7 4 QNQ
Q17 15 20 3 QPQ
C15 21 22 4.8E-12
R69 12 21 3
R70 12 15 3E9
E2 23 8 3 0 -10E-6
V51 23 1 1.56E-3
I6 3 4 5E-6
R71 4 3 4.5E5
Q18 12 9 11 QPQ
Q19 13 10 11 QPQ
C17 12 13 8E-12
C18 6 15 1E-12
C21 3 24 100E-15
R78 11 24 3E5
C22 1 2 0.23E-12
C23 2 0 0.79E-12
C24 1 0 0.79E-12
E3 22 0 15 0 2
C25 5 0 50E-15
Q20 25 25 0 QNQ
G1 3 4 VT 0 3E-4
I7 0 25 1E-3
V53 25 26 0.25
R79 0 26 1E6
E4 VT 0 27 26 1
R80 0 VT 1E6
V54 27 0 0.55
R81 0 27 1E6
.MODEL QPQ PNP IKF=3E-3 RC=300 KF=4.8E-17 BR=1
.MODEL QPA PNP IKF=3E-3 RC=380 IS=1.01E-16 VAF=245 RE=5 RB=1700 BF=300 KF=4.8E-17 BR=1
.MODEL QPI PNP IKF=3E-3 RC=380 IS=1.01E-16 VAF=290 RE=5 RB=1700 BF=306 KF=4.8E-17 BR=1
.MODEL QNQ NPN IKF=5E-3 RC=25 KF=4.8E-17 BR=1
.ENDS
* END SPICE MODEL LM358
.MODEL Q2N2222 NPN (
+ IS = 3.97589E-14 BF = 195.3412 NF = 1.0040078 VAF = 53.081 IKF = 0.976 ISE = 1.60241E-14
+ NE = 1.4791931 BR = 1.1107942 NR = 0.9928261 VAR = 11.3571702 IKR = 2.4993953 ISC = 1.88505E-12
+ NC = 1.1838278 RB = 56.5826472 IRB = 1.50459E-4 RBM = 5.2592283 RE = 0.0402974 RC = 0.4208
+ CJE = 2.56E-11 VJE = 0.682256 MJE = 0.3358856 TF = 3.3E-10 XTF = 6 VTF = 0.574
+ ITF = 0.32 PTF = 25.832 CJC = 1.40625E-11 VJC = 0.5417393 MJC = 0.4547893 XCJC = 1
+ TR = 3.2E-7 CJS = 0 VJS = .75 MJS = 0 XTB = 1.6486 EG = 1.11
+ XTI = 5.8315 KF = 0 AF = 1 FC = 0.83
+ vce_max=45 vbe_max=6 )

View File

@ -1,122 +0,0 @@
.MODEL BC857 PNP(
+ AF= 1.00E+00 BF= 1.96E+02 BR= 3.38E+00 CJC= 9.80E-12
+ CJE= 1.56E-11 CJS= 0.00E+00 EG= 1.11E+00 FC= 8.28E-01
+ IKF= 8.35E-01 IKR= 1.60E-02 IRB= 1.31E-06 IS= 1.32E-14
+ ISC= 7.71E-14 ISE= 8.44E-13 ITF= 2.14E-01 KF= 0.00E+00
+ MJC= 3.49E-01 MJE= 4.18E-01 MJS= 3.30E-01 NC= 1.19E+00
+ NE= 1.83E+00 NF= 1.00E+00 NR= 1.00E+00 PTF= 0.00E+00
+ RB= 1.00E-02 RBM= 1.00E-02 RC= 1.52E+00 RE= 3.00E-02
+ TF= 6.05E-10 TR= 0.00E+00 VAF= 5.90E+01 VAR= 1.74E+01
+ VJC= 3.00E-01 VJE= 8.00E-01 VJS= 7.50E-01 VTF= 4.39E+00
+ XCJC= 1.00E+00 XTB= 0.00E+00 XTF= 5.81E+00 XTI= 3.00E+00)
.SUBCKT irlml6402 1 2 3
* Node 1 -> Drain
* Node 2 -> Gate
* Node 3 -> Source
M1 9 7 8 8 MM L=100u W=100u
.MODEL MM PMOS LEVEL=1 IS=1e-32
+VTO=-1 LAMBDA=0.0111358 KP=12.788
+CGSO=5.36099e-06 CGDO=5.54234e-08
RS 8 3 0.0246704
D1 1 3 MD
.MODEL MD D IS=2.03395e-08 RS=0.0432758 N=1.5 BV=20
+IBV=0.00025 EG=1 XTI=4 TT=1e-07
+CJO=1.11974e-10 VJ=0.5 M=0.3 FC=0.5
RDS 3 1 5e+07
RD 9 1 0.0001
RG 2 7 29.2227
D2 5 4 MD1
* Default values used in MD1:
* RS=0 EG=1.11 XTI=3.0 TT=0
* BV=infinite IBV=1mA
.MODEL MD1 D IS=1e-32 N=50
+CJO=1.68841e-10 VJ=1.50027 M=0.3 FC=1e-08
D3 5 0 MD2
* Default values used in MD2:
* EG=1.11 XTI=3.0 TT=0 CJO=0
* BV=infinite IBV=1mA
.MODEL MD2 D IS=1e-10 N=0.4 RS=3e-06
RL 5 10 1
FI2 7 9 VFI2 -1
VFI2 4 0 0
EV16 10 0 9 7 1
CAP 11 10 9.68769e-10
FI1 7 9 VFI1 -1
VFI1 11 6 0
RCAP 6 10 1
D4 6 0 MD3
* Default values used in MD3:
* EG=1.11 XTI=3.0 TT=0 CJO=0
* RS=0 BV=infinite IBV=1mA
.MODEL MD3 D IS=1e-10 N=0.4
.ENDS irlml6402
.SUBCKT D1N5765 2 99
* | |
* | |
* | CATHODE
* ANODE
I1 99 4 7.0
D1 2 99 DLOW
D2 2 4 DHIGH
R1 4 99 .1 TC=-6.27E-3,-2.33E-7
*
.MODEL DLOW D (
+ IS = 1.0E-15
+ RS = 100
+ N = 2.15
+ TT = 10.0E-09
+ CJO = 8.285237E-11
+ VJ = 1.2076937
+ M = 0.4053107
+ EG = 1.664
+ XTI = 10.78
+ KF = 0
+ AF = 1
+ FC = 0.4340008
+ BV = 5.0
+ IBV = 1E-4
+ )
.MODEL DHIGH D (
+ IS = 9.0E-15
+ RS = 0.30
+ N = 1.2
+ TT = 0
+ CJO = 0
+ VJ = 1
+ M = .5
+ EG = 0.1
+ XTI = -3.84
+ KF = 0
+ AF = 1
+ FC = .5
+ BV = 9.9999E+13
+ IBV = .001
+ )
.ENDS
.SUBCKT BZX5V1 a c
DF a c DFOR
DR c a DREV
DB b a DBRE
EB c b POLY(1) d 0 3.6 1
IB 0 d 1m
RB 0 d 1k TC=3m
.MODEL DFOR D
+ IS = 1p RS = 3.5 N = 1.4 CJO= 178p
+ VJ = 610m M = 335m FC = 700m XTI= 3
+ EG =1.186
.MODEL DREV D
+ IS = 100f N = 30 XTI= 3 EG =1.186
.MODEL DBRE D
+ IS = 10f RS = 6 N = 1 XTI= 0
+ EG =1.186
.ENDS BZX5V1

View File

@ -1,95 +0,0 @@
.model cmosn NMOS
+ Level = 49
+ Lint = 4.e-08 Tox = 4.e-09
+ Vth0 = 0.3999 Rdsw = 250
+ lmin=1.8e-7 lmax=1.8e-7 wmin=1.8e-7 wmax=1.0e-4 Tref=27.0 version =3.1
+ Xj= 6.0000000E-08 Nch= 5.9500000E+17
+ lln= 1.0000000 lwn= 1.0000000 wln= 0.00
+ wwn= 0.00 ll= 0.00
+ lw= 0.00 lwl= 0.00 wint= 0.00
+ wl= 0.00 ww= 0.00 wwl= 0.00
+ Mobmod= 1 binunit= 2 xl= 0
+ xw= 0 binflag= 0
+ Dwg= 0.00 Dwb= 0.00
+ K1= 0.5613000 K2= 1.0000000E-02
+ K3= 0.00 Dvt0= 8.0000000 Dvt1= 0.7500000
+ Dvt2= 8.0000000E-03 Dvt0w= 0.00 Dvt1w= 0.00
+ Dvt2w= 0.00 Nlx= 1.6500000E-07 W0= 0.00
+ K3b= 0.00 Ngate= 5.0000000E+20
+ Vsat= 1.3800000E+05 Ua= -7.0000000E-10 Ub= 3.5000000E-18
+ Uc= -5.2500000E-11 Prwb= 0.00
+ Prwg= 0.00 Wr= 1.0000000 U0= 3.5000000E-02
+ A0= 1.1000000 Keta= 4.0000000E-02 A1= 0.00
+ A2= 1.0000000 Ags= -1.0000000E-02 B0= 0.00
+ B1= 0.00
+ Voff= -0.12350000 NFactor= 0.9000000 Cit= 0.00
+ Cdsc= 0.00 Cdscb= 0.00 Cdscd= 0.00
+ Eta0= 0.2200000 Etab= 0.00 Dsub= 0.8000000
+ Pclm= 5.0000000E-02 Pdiblc1= 1.2000000E-02 Pdiblc2= 7.5000000E-03
+ Pdiblcb= -1.3500000E-02 Drout= 1.7999999E-02 Pscbe1= 8.6600000E+08
+ Pscbe2= 1.0000000E-20 Pvag= -0.2800000 Delta= 1.0000000E-02
+ Alpha0= 0.00 Beta0= 30.0000000
+ kt1= -0.3700000 kt2= -4.0000000E-02 At= 5.5000000E+04
+ Ute= -1.4800000 Ua1= 9.5829000E-10 Ub1= -3.3473000E-19
+ Uc1= 0.00 Kt1l= 4.0000000E-09 Prt= 0.00
+ Cj= 0.00365 Mj= 0.54 Pb= 0.982
+ Cjsw= 7.9E-10 Mjsw= 0.31 Php= 0.841
+ Cta= 0 Ctp= 0 Pta= 0
+ Ptp= 0 JS=1.50E-08 JSW=2.50E-13
+ N=1.0 Xti=3.0 Cgdo=2.786E-10
+ Cgso=2.786E-10 Cgbo=0.0E+00 Capmod= 2
+ NQSMOD= 0 Elm= 5 Xpart= 1
+ Cgsl= 1.6E-10 Cgdl= 1.6E-10 Ckappa= 2.886
+ Cf= 1.069e-10 Clc= 0.0000001 Cle= 0.6
+ Dlc= 4E-08 Dwc= 0 Vfbcv= -1
*
* Predictive Technology Model Beta Version
* 180nm PMOS SPICE Parametersv (normal one)
*
.model cmosp PMOS
+ Level = 49
+ Lint = 3.e-08 Tox = 4.2e-09
+ Vth0 = -0.42 Rdsw = 450
+ lmin=1.8e-7 lmax=1.8e-7 wmin=1.8e-7 wmax=1.0e-4 Tref=27.0 version =3.1
+ Xj= 7.0000000E-08 Nch= 5.9200000E+17
+ lln= 1.0000000 lwn= 1.0000000 wln= 0.00
+ wwn= 0.00 ll= 0.00
+ lw= 0.00 lwl= 0.00 wint= 0.00
+ wl= 0.00 ww= 0.00 wwl= 0.00
+ Mobmod= 1 binunit= 2 xl= 0.00
+ xw= 0.00
+ binflag= 0 Dwg= 0.00 Dwb= 0.00
+ ACM= 0 ldif=0.00 hdif=0.00
+ rsh= 0 rd= 0 rs= 0
+ rsc= 0 rdc= 0
+ K1= 0.5560000 K2= 0.00
+ K3= 0.00 Dvt0= 11.2000000 Dvt1= 0.7200000
+ Dvt2= -1.0000000E-02 Dvt0w= 0.00 Dvt1w= 0.00
+ Dvt2w= 0.00 Nlx= 9.5000000E-08 W0= 0.00
+ K3b= 0.00 Ngate= 5.0000000E+20
+ Vsat= 1.0500000E+05 Ua= -1.2000000E-10 Ub= 1.0000000E-18
+ Uc= -2.9999999E-11 Prwb= 0.00
+ Prwg= 0.00 Wr= 1.0000000 U0= 8.0000000E-03
+ A0= 2.1199999 Keta= 2.9999999E-02 A1= 0.00
+ A2= 0.4000000 Ags= -0.1000000 B0= 0.00
+ B1= 0.00
+ Voff= -6.40000000E-02 NFactor= 1.4000000 Cit= 0.00
+ Cdsc= 0.00 Cdscb= 0.00 Cdscd= 0.00
+ Eta0= 8.5000000 Etab= 0.00 Dsub= 2.8000000
+ Pclm= 2.0000000 Pdiblc1= 0.1200000 Pdiblc2= 8.0000000E-05
+ Pdiblcb= 0.1450000 Drout= 5.0000000E-02 Pscbe1= 1.0000000E-20
+ Pscbe2= 1.0000000E-20 Pvag= -6.0000000E-02 Delta= 1.0000000E-02
+ Alpha0= 0.00 Beta0= 30.0000000
+ kt1= -0.3700000 kt2= -4.0000000E-02 At= 5.5000000E+04
+ Ute= -1.4800000 Ua1= 9.5829000E-10 Ub1= -3.3473000E-19
+ Uc1= 0.00 Kt1l= 4.0000000E-09 Prt= 0.00
+ Cj= 0.00138 Mj= 1.05 Pb= 1.24
+ Cjsw= 1.44E-09 Mjsw= 0.43 Php= 0.841
+ Cta= 0.00093 Ctp= 0 Pta= 0.00153
+ Ptp= 0 JS=1.50E-08 JSW=2.50E-13
+ N=1.0 Xti=3.0 Cgdo=2.786E-10
+ Cgso=2.786E-10 Cgbo=0.0E+00 Capmod= 2
+ NQSMOD= 0 Elm= 5 Xpart= 1
+ Cgsl= 1.6E-10 Cgdl= 1.6E-10 Ckappa= 2.886
+ Cf= 1.058e-10 Clc= 0.0000001 Cle= 0.6
+ Dlc= 3E-08 Dwc= 0 Vfbcv= -1

View File

@ -1,473 +0,0 @@
#!/usr/bin/perl
# -*- perl -*-
# Copyright (C) 2006 DJ Delorie dj@delorie.com
# Released under the terms of the GNU General Public License, version 2
# Usage: djboxsym sample.symdef > sample.sym
$y{left} = 400;
$y{right} = 400;
$y{labels} = 600;
$labelpin = 0;
$busspace = 200;
$groupspace = 400;
$skipspace = 800;
$yinvert = 300;
$minwidth = 0;
# If set, top and bottom labels are vertical.
$vmode = 0;
# Read in the file, storing information about each pin.
while (<>) {
next if /^#/;
s/^\s+//;
s/\s+$//;
s/[\s\t]+/ /g;
s/[\r\n]+$//;
# options
if (/^--(\S*)\s*(.*)/) {
$opt = $1;
@args = split(' ', $2);
($opt, $value) = split(' ', $opt, 2);
if ($opt eq "vmode") {
$vmode = 1;
# $y{left} = $y{right} = 0;
}
if ($opt eq "square") {
$square = 1;
}
if ($opt eq "minwidth") {
$minwidth = $args[0];
}
if ($opt eq "compact") {
$groupspace = 200;
$skipspace = 400;
$yinvert = 400;
$compactmode = 1;
}
next;
}
# Note change of section.
if (/^\[(.*)\]/) {
$side = $1;
$space = 0;
next;
}
# Start a bus
if (/^\.bus/) {
$busmode = 1;
next;
}
# blank lines - cancel bus, add gap.
if (! /\S/) {
if ($busmode) {
$y{$side} += $busspace;
}
$busmode = 0;
if ($space) {
if ($side =~ /left|right/) {
$y{$side} += $groupspace;
}
if ($side =~ /top|bottom/) {
$x{$side} += 400;
}
$space = 0;
}
next;
}
if (/^\.skip (\d+)/) {
$skip = $1;
$space = 0;
if ($side =~ /left|right/) {
$y{$side} += $skip;
}
next;
}
# Hidden labels are stored separately, because we don't care how
# big they are.
if (/! (\S.*)/ && $side eq "labels") {
push(@attrs, $1);
next;
}
# Visible labels are stored as pins because their size affects the
# size of the symbols' box.
if (/\S/ && $side eq "labels") {
$labelpin --;
$pinside{$labelpin} = $side;
$piny{$labelpin} = $y{labels};
$pinlabel{$labelpin} = $_;
$y{labels} += $groupspace;
$rlen{$labelpin} = &textlen($_);
next;
}
# Regular pins are handled here.
if (/^(\S+)\s*(.*)/) {
$space = 1;
($pin, $rest) = ($1,$2);
if ($pin =~ /^\d+$/) {
$pinseq_used[$pin] = 1;
}
if ($saw_pin{$pin}) {
print STDERR "DUPLICATE PIN $pin (was $pinlabel{$pin}, now $rest)\n";
$errors ++;
}
$saw_pin{$pin} = 1;
$maxpin = $pin if $maxpin < $pin;
$pinside{$pin} = $side;
$pintype{$pin} = "pas";
next if $side eq "nc";
if ($rest =~ /^([!>iop]+) (.*)/) {
$flags = $1;
$pinlabel{$pin} = $2;
$bubble{$pin} = 1 if $flags =~ /!/;
$edge{$pin} = 1 if $flags =~ />/;
$pintype{$pin} = "in" if $flags =~ /i/;
$pintype{$pin} = "out" if $flags =~ /o/;
$pintype{$pin} = "pwr" if $flags =~ /p/;
$pintype{$pin} = "inout" if $flags =~ /io/;
} else {
$pinlabel{$pin} = $rest;
}
$rlen{$pin} = &textlen($pinlabel{$pin});
if ($side =~ /left|right/) {
$y = $piny{$pin} = $y{$side};
$y{$side} += ($busmode ? $busspace : $groupspace);
}
if ($side =~ /top|bottom/) {
$tw = &alignpin((200 + $rlen{$pin}) / 2);
if ($vmode) {
$pinx{$pin} = $w{$side};
$w{$side} += (($busmode || $compactmode) ? 200 : 400);
} else {
$pinx{$pin} = $w{$side} + $tw;
$w{$side} += $tw + $tw;
}
}
}
}
$pinseq = 1;
$minpin = $labelpin;
$boxwidth = $minwidth;
%bw = ();
# for each horizontal slice of the symbol, keep track of how much
# width is used up by the left, middle, and right labels.
for $lp (keys %pinside) {
next unless $pinside{$lp} =~ /left|right|label/;
$yb = &alignpin($piny{$lp});
for ($y=$yb-300; $y<=$yb+300; $y+=100) {
if ($bw{$y}{$pinside{$lp}} < $rlen{$lp}) {
$bw{$y}{$pinside{$lp}} = $rlen{$lp};
}
}
}
# Compute the height of the box.
for $p (keys %pinside) {
next unless $pinside{$p} =~ /left|right/;
if ($maxy < $piny{$p}) {
$maxy = $piny{$p};
}
}
if (! $vmode) {
$maxy += $groupspace;
}
# Now, use the slice widths to compute the minimum width of the box.
for ($i=0; $i<$maxy; $i+=100) {
$w = $bw{$i}{left} + $bw{$i}{labels} + $bw{$i}{right};
if ($bw{$i}{labels}) {
$wl = ($bw{$i}{left} + $bw{$i}{labels}/2) * 2;
$w = $wl if $w < $wl;
$wl = ($bw{$i}{right} + $bw{$i}{labels}/2) * 2;
$w = $wl if $w < $wl;
}
if ($bw{$i}{left} && $bw{$i}{labels}) {
$w += 100;
} elsif ($bw{$i}{left} && $bw{$i}{right}) {
$w += 200;
}
if ($bw{$i}{right} && $bw{$i}{labels}) {
$w += 100;
}
if ($boxwidth < $w) {
$boxwidth = $w;
}
}
$boxwidth = $w{top} if $boxwidth < $w{top};
$boxwidth = $w{bottom} if $boxwidth < $w{bottom};
# Flip Y coordinates (we count from the top, but symbols coordinates
# are from the bottom).
for $p (keys %pinside) {
next unless $pinside{$p} =~ /left|right|labels/;
$piny{$p} = $maxy - $piny{$p} + $yinvert;
}
$boxwidth = &alignpin($boxwidth);
$boxwidth += 200;
# Adjust the position of the top/bottom pins so that, as a group,
# they're centered.
%maxh = ();
for $p (keys %pinside) {
next unless $pinside{$p} =~ /top|bottom/;
$pinx{$p} += &alignpin(($boxwidth - $w{$pinside{$p}})/2) + 300;
if ($vmode) {
$pinx{$p} += 200;
$h = &textlen($pinlabel{$p});
$maxh{$pinside{$p}} = $h if $maxh{$pinside{$p}} < $h;
}
}
if ($vmode) {
$dy = &alignpin($maxh{bottom});
for $lp ($minpin..-1) {
$piny{$lp} += $dy;
}
for $p (keys %pinside) {
if ($pinside{$p} =~ /left|right|bottom/) {
$piny{$p} += $dy;
}
}
$maxy += $dy + &alignpin ($maxh{top});
}
if ($square) {
if ($boxwidth < $maxy) {
$delta = $maxy - $boxwidth;
$delta = &alignpin($delta / 2);
$boxwidth = $maxy;
for $p (keys %pinside) {
if ($pinside{$p} =~ /top|bottom/) {
$pinx{$p} += $delta;
}
}
}
if ($maxy < $boxwidth) {
$maxy = $boxwidth;
}
}
# Labels are centered in the box.
for $lp ($minpin..-1) {
$pinx{$lp} = &alignpin($boxwidth/2) + 300;
}
# Version.
print "v 20060123 1\n";
# Symbol box.
printf("B %d %d %d %d 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1\n",
300, 300, $boxwidth, $maxy);
# These are the hidden labels.
$ax = 300 + $boxwidth;
$ay = 400 + $maxy;
for $a (reverse @attrs) {
printf("T %d %d 9 10 0 0 0 0 1\n%s\n",
$ax, $ay, $a);
$ay += 200;
}
sub pinsort {
my ($a, $b) = @_;
$a =~ tr/a-z/A-Z/;
$b =~ tr/a-z/A-Z/;
$a =~ s/(\d+)/sprintf("%06d", $1);/ge;
$b =~ s/(\d+)/sprintf("%06d", $1);/ge;
return $a cmp $b;
}
# Now print all the pins.
for $p (sort {&pinsort($a,$b)} keys %pinside) {
next unless $pinside{$p};
if ($pinside{$p} eq "left") {
$pinx{$p} = 300;
}
if ($pinside{$p} eq "right") {
$pinx{$p} = 300 + $boxwidth;
}
if ($p > 0 && !$saw_pin{$p}) {
print STDERR "MISSING PIN $p\n";
$errors++;
} else {
printf STDERR ("%3s %-6s %4d %4d %s\n",
$p, $pinside{$p}, $pinx{$p}, $piny{$p}, $pinlabel{$p});
}
eval "&drawpin_$pinside{\"$p\"} (\"$p\")";
}
# what remains are helper functions; for drawing each type of pin,
# each type of label, etc.
sub drawpin_nc {
}
sub drawpin_top {
my($pin) = @_;
$y = $maxy + 300;
printf("P %d %d %d %d 1 0 0\n",
$pinx{$pin}, $y+300, $pinx{$pin}, $y);
print "{\n";
if ($vmode) {
&pvltext($pinx{$pin}, $y-50, 7, $pinlabel{$pin});
} else {
&pltext($pinx{$pin}, $y-50, 5, $pinlabel{$pin});
}
&ntext($pinx{$pin}+50, $y+50, 0, $pin);
&pttext($pinx{$pin} -100, $piny{$pin} + 50, 6, $pintype{$pin});
print "}\n";
}
sub drawpin_bottom {
my($pin) = @_;
printf("P %d %d %d %d 1 0 0\n",
$pinx{$pin}, 0, $pinx{$pin}, 300);
print "{\n";
if ($vmode) {
&pvltext($pinx{$pin}, 350, 1, $pinlabel{$pin});
} else {
&pltext($pinx{$pin}, 350, 3, $pinlabel{$pin});
}
&ntext($pinx{$pin}+50, 250, 2, $pin);
&pttext($pinx{$pin} -100, $piny{$pin} + 50, 6, $pintype{$pin});
print "}\n";
}
sub drawpin_labels {
my($pin) = @_;
&ltext($pinx{$pin}, $piny{$pin}, 3, $pinlabel{$pin});
}
sub circle {
my ($x, $y) = @_;
print "V $x $y 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1\n";
}
sub drawpin_left {
my($pin) = @_;
$x = $pinx{$pin};
$px = 50;
if ($bubble{$pin}) {
$x -= 100;
&circle($x+50, $piny{$pin});
}
if ($edge{$pin}) {
$px += 100;
printf("L %d %d %d %d 3 0 0 0 0 0\n",
$pinx{$pin}, $piny{$pin}-50,
$pinx{$pin}+100, $piny{$pin});
printf("L %d %d %d %d 3 0 0 0 0 0\n",
$pinx{$pin}+100, $piny{$pin},
$pinx{$pin}, $piny{$pin}+50);
}
printf("P %d %d %d %d 1 0 0\n",
$pinx{$pin} - 300, $piny{$pin}, $x, $piny{$pin});
print "{\n";
&pltext($pinx{$pin} + $px, $piny{$pin}, 1, $pinlabel{$pin});
&ntext($pinx{$pin} -100, $piny{$pin} + 50, 6, $pin);
&pttext($pinx{$pin} -100, $piny{$pin} + 50, 6, $pintype{$pin});
print "}\n";
}
sub drawpin_right {
my($pin) = @_;
$x = $pinx{$pin};
$px = 50;
if ($bubble{$pin}) {
$x += 100;
&circle($x-50, $piny{$pin});
}
if ($edge{$pin}) {
$px += 100;
printf("L %d %d %d %d 3 0 0 0 0 0\n",
$pinx{$pin}, $piny{$pin}-50,
$pinx{$pin}-100, $piny{$pin});
printf("L %d %d %d %d 3 0 0 0 0 0\n",
$pinx{$pin}-100, $piny{$pin},
$pinx{$pin}, $piny{$pin}+50);
}
printf("P %d %d %d %d 1 0 0\n",
$pinx{$pin} + 300, $piny{$pin}, $x, $piny{$pin});
print "{\n";
&pltext($pinx{$pin} - $px, $piny{$pin}, 7, $pinlabel{$pin});
&ntext($pinx{$pin} +100, $piny{$pin} + 50, 0, $pin);
&pttext($pinx{$pin} -100, $piny{$pin} + 50, 6, $pintype{$pin});
print "}\n";
}
sub ntext {
my ($x, $y, $a, $s) = @_;
printf("T %d %d 5 8 1 1 0 %s 1\npinnumber=%s\n", $x, $y, $a, $s);
if ($s =~ /^\d+$/) {
$my_pinseq = $s;
} else {
while ($pinseq_used[$pinseq]) {
$pinseq ++;
}
$pinseq_used[$pinseq] = 1;
$my_pinseq = $pinseq;
}
printf("T %d %d 5 8 0 1 0 %s 1\npinseq=%d\n", $x, $y, $a, $my_pinseq);
}
sub pttext {
my ($x, $y, $a, $s) = @_;
printf("T %d %d 9 10 0 1 0 %s 1\npintype=%s\n", $x, $y, $a, $s);
}
sub pltext {
my ($x, $y, $a, $s) = @_;
$s = "pinlabel=$s" unless $s =~ /=/;
printf("T %d %d 9 10 1 1 0 %s 1\n%s\n", $x, $y, $a, $s);
}
sub pvltext {
my ($x, $y, $a, $s) = @_;
$s = "pinlabel=$s" unless $s =~ /=/;
printf("T %d %d 9 10 1 1 90 %s 1\n%s\n", $x, $y, $a, $s);
}
sub ltext {
my ($x, $y, $a, $s) = @_;
printf("T %d %d 9 10 1 1 0 %s 1\n%s\n", $x, $y, $a, $s);
}
sub textlen {
my($t) = @_;
$t =~ s/^[^=]*=//;
$t =~ s@\\_@@g;
return length($t) * 110;
}
sub alignpin {
my($v) = @_;
return int(($v + 99) / 100) * 100;
}
exit $errors;

View File

@ -1,16 +0,0 @@
v {xschem version=2.9.2 file_version=1.1}
G {type=subcircuit
format="@name @pinlist @symname"
template="name=X1"}
B 5 137.5 -22.5 142.5 -17.5 {name=Z dir=out pinnumber=1}
L 2 100 -20 140 -20 {}
T {Z} 89 -29.6 0 1 0.4 0.4 {}
B 5 -142.5 -22.5 -137.5 -17.5 {name=A dir=in pinnumber=2}
L 4 -140 -20 -100 -20 {}
T {A} -89 -29.6 0 0 0.4 0.4 {}
B 5 -142.5 17.5 -137.5 22.5 {name=B dir=in pinnumber=3}
L 4 -140 20 -100 20 {}
T {B} -89 10.4 0 0 0.4 0.4 {}
P 4 5 -100 -80 100 -80 100 80 -100 80 -100 -80 {}
T {@name} -45 -28 0 0 0.6 0.6 {}
T {@symname} -72 12 0 0 0.6 0.6 {}

View File

@ -1,13 +0,0 @@
[labels]
--hide-pinnumber
--auto-pinnumber
@name
@symname
! type=subcircuit
! format="@name @pinlist @symname"
! template="name=X1"
[right]
o Z
[left]
i A
i B

View File

@ -1,28 +0,0 @@
v {xschem version=2.9.2 file_version=1.1}
G {type=subcircuit
format="@name @pinlist @model"
template="name=X1"}
B 5 -242.5 -42.5 -237.5 -37.5 {name=D dir=in pinnumber=1}
L 4 -240 -40 -200 -40 {}
T {D} -189 -49.6 0 0 0.4 0.4 {}
B 5 -242.5 -2.5 -237.5 2.5 {name=RST dir=in pinnumber=2}
L 4 -240 0 -200 0 {}
T {RST} -189 -9.6 0 0 0.4 0.4 {}
B 5 -242.5 37.5 -237.5 42.5 {name=CLK dir=in pinnumber=3}
L 4 -240 40 -210 40 {}
T {CLK} -189 30.4 0 0 0.4 0.4 {}
A 4 -205 40 5 0 360 {}
L 4 -200 32 -192 40 {}
L 4 -200 48 -192 40 {}
B 5 237.5 -42.5 242.5 -37.5 {name=QB dir=out pinnumber=4}
L 2 200 -40 240 -40 {}
T {QB} 189 -49.6 0 1 0.4 0.4 {}
B 5 -162.5 -142.5 -157.5 -137.5 {name=VCC dir=inout pinnumber=5}
L 3 -160 -140 -160 -100 {}
T {VCC} -181 -89 0 0 0.4 0.4 {}
B 5 -162.5 137.5 -157.5 142.5 {name=VSS dir=inout pinnumber=6}
L 3 -160 100 -160 140 {}
T {VSS} -181 89 2 1 0.4 0.4 {}
P 4 5 -200 -100 200 -100 200 100 -200 100 -200 -100 {}
T {TEST SYMBOL} -99 -28 0 0 0.6 0.6 {}
T {STEFAN SCHIPPERS} -144 12 0 0 0.6 0.6 {}