Stefan Frederik 0d6a6c488b handle spice simulation files with multiple datasets		2021-12-25 05:15:52 +01:00
..
binto7seg	add -pg also in LDFLAGS if --profile is requested; add little more margin in ps page exports	2021-01-06 00:12:04 +01:00
devices	swap s/d in verilog netlisting rule for enhancement load "rnmos4.sym" so it can be used as usually done with nmos devices (drain side up) .	2021-12-01 15:53:14 +01:00
examples	handle spice simulation files with multiple datasets	2021-12-25 05:15:52 +01:00
gschem_import	some parameter checks in xschem commands, global var removal in simulation help window - No use for production yet	2021-11-16 22:28:10 +01:00
logic	preserve ordering in verilog/VHDL signal/wire/reg declarations for consistent netlist hashing/checking	2021-12-15 15:17:45 +01:00
ngspice	handle spice simulation files with multiple datasets	2021-12-25 05:15:52 +01:00
pcb	Windows does not recognize XPending, fix typo for verilog_format`s port name: g instead of f	2021-11-26 13:16:52 +01:00
rom8k	handle spice simulation files with multiple datasets	2021-12-25 05:15:52 +01:00
rulz-r8c33	"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols	2020-09-30 00:30:48 +02:00
symgen	removed unused files	2020-08-24 10:01:41 +02:00
xTAG	populating xschem git repo	2020-08-08 15:47:34 +02:00
xschem_simulator	added missing symbols	2021-12-19 01:32:19 +01:00
Makefile	added "xschem_simulator" sample example directory for trying logic propagation of probed nets	2020-12-26 19:26:33 +01:00