preserve ordering in verilog/VHDL signal/wire/reg declarations for consistent netlist hashing/checking
This commit is contained in:
Stefan Frederik
parent
95ea920faf
commit
ba15e21b24
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@ -1045,7 +1045,9 @@ static void send_current_to_gaw(int simtype, const char *node)
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my_free(1182, &t);
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}
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/* hilight_instances: if set == 1 hilight non pin/label symbols with "highlight=true" attribute set */
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/* hilight/clear pin/label instances attached to hilight nets, or instances with "hilight=true"
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* attr if en_hilight_conn_inst option is set
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*/
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void propagate_hilights(int set, int clear, int mode)
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{
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int i, hilight_connected_inst;
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@ -1058,12 +1060,14 @@ void propagate_hilights(int set, int clear, int mode)
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prepare_netlist_structs(0);
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for(i = 0; i < xctx->instances; i++) {
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if(xctx->inst[i].ptr < 0 ) {
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dbg(0, "propagate_hilights(): .ptr < 0, unbound symbol: inst %d, name=%s\n", i, xctx->inst[i].instname);
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dbg(0, "propagate_hilights(): .ptr<0, unbound symbol: inst %d, name=%s sch=%s\n",
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i, xctx->inst[i].instname, xctx->current_name);
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continue;
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}
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type = (xctx->inst[i].ptr+ xctx->sym)->type;
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hilight_connected_inst = en_hi &&
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( (xctx->inst[i].flags & 4) || ((xctx->inst[i].ptr+ xctx->sym)->flags & 4) );
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/* hilight/clear instances with hilight=true attr set and en_hilight_conn_inst option is set ... */
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if(hilight_connected_inst && type && !IS_LABEL_SH_OR_PIN(type)) {
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int rects, j, nohilight_pins;
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if( (rects = (xctx->inst[i].ptr+ xctx->sym)->rects[PINLAYER]) > 0 ) {
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@ -1085,6 +1089,7 @@ void propagate_hilights(int set, int clear, int mode)
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xctx->inst[i].color=-10000;
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}
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}
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/* ... else hilight/clear pin/label instances attached to hilight nets */
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} else if(type && xctx->inst[i].node && IS_LABEL_SH_OR_PIN(type) ) {
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entry=bus_hilight_hash_lookup( xctx->inst[i].node[0], 0, XLOOKUP);
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if(entry && set) xctx->inst[i].color = entry->value;
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@ -1137,7 +1137,7 @@ void load_schematic(int load_symbols, const char *filename, int reset_undo) /* 2
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}
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if(tclgetboolvar("autotrim_wires")) trim_wires();
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update_conn_cues(0, 0);
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if(xctx->hilight_nets) {
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if(xctx->hilight_nets && load_symbols) {
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propagate_hilights(1, 1, XINSERT_NOREPLACE);
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}
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}
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@ -38,6 +38,7 @@ BEGIN{
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net_types["integer"]=1
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net_types["time"]=1
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net_types["real"]=1
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net_types["signed"]=1
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net_types["logic"]=1
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net_types["bool"]=1
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direction["input"]=1
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@ -108,7 +109,8 @@ primitive==1{primitive_line=primitive_line " " $0; next }
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# print signals/regs/variables
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/---- end signal list/{
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for(i in signal_basename) {
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for(ii = 0 ; ii < signal_n; ii++) { # used to preserve order of signals
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i = signal_num[ii] # used to preserve order of signals
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n=signal_basename[i]
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split(signal_index[i],tmp)
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hsort(tmp,n)
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@ -150,8 +152,7 @@ primitive==1{primitive_line=primitive_line " " $0; next }
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# store signals
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siglist==1 && ($1 in net_types) {
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# 20070525 recognize "reg real" types and similar
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# 20070525 recognize "reg real", "wire signed" types and similar
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if($2 in net_types) {
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if($3 ~ /^#/) basename=s_b($4)
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else basename=s_b($3)
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@ -166,20 +167,19 @@ siglist==1 && ($1 in net_types) {
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sub(/;.*/,"",val)
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signal_value[basename]=val
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}
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if(!(basename in signal_basename)) signal_num[signal_n++] = basename # used to preserve order of signals
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signal_basename[basename]++
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if($3 ~ /\[.*\]/) {
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signal_index[basename]=signal_index[basename] " " s_i($3)
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}
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else signal_index[basename]="no_index"
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}
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# /20070525
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# /20070525
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else {
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if($2 ~ /^#/) basename=s_b($3)
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else basename=s_b($2)
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signal_type[basename]=$1
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if($2 ~ /^#/) {
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if($2 ~ /^#/) { # handle declarations like: wire #20 w_tmp;
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signal_delay[basename]=$2
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$2=""; $0=$0;
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}
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@ -189,6 +189,7 @@ siglist==1 && ($1 in net_types) {
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sub(/;.*/,"",val)
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signal_value[basename]=val
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}
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if(!(basename in signal_basename)) signal_num[signal_n++] = basename # used to preserve order of signals
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signal_basename[basename]++
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if($2 ~ /\[.*\]/) {
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signal_index[basename]=signal_index[basename] " " s_i($2)
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@ -216,6 +217,8 @@ NF==3 && $3=="(" && $1=="module" {
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delete signal_value
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delete signal_type
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delete signal_delay
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delete signal_num # used to preserve order of signals
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signal_n = 0 # used to preserve order of signals
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}
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begin_module && $1 ~/^\);$/ {
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@ -399,8 +399,6 @@ void verilog_block_netlist(FILE *fd, int i)
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fprintf(fd, "// sym_path: %s\n", abs_sym_path(xctx->sym[i].name, ""));
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fprintf(fd, "// sch_path: %s\n", filename);
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verilog_stop? load_schematic(0,filename, 0) : load_schematic(1,filename, 0);
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/* print verilog timescale and preprocessor directives 10102004 */
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for(j=0;j<xctx->instances;j++)
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142
src/vhdl.awk
142
src/vhdl.awk
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@ -207,6 +207,8 @@ primitive==1{primitive_line=primitive_line " " $0; next } # 20071217
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/^[ \t]*architecture[ \t]+.*[ \t]+is[ \t]*$/{
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arch_rep=$2
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arch=$4
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arch_signal_n = 0 # used to preserve order of signals
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delete arch_signal_num # used to preserve order of signals
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delete arch_signal_dir
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delete arch_index_array
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delete arch_sig_type_array
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@ -250,6 +252,9 @@ primitive==1{primitive_line=primitive_line " " $0; next } # 20071217
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sig_dir=" downto " # just to have a value
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sig_class=$1
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}
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if(!(sig_basename in arch_signal_dir)) {
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arch_signal_num[arch_signal_n++] = sig_basename # used to preserve order of signals
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}
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arch_signal_dir[sig_basename]=sig_dir
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arch_signal_class[sig_basename]=sig_class
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arch_sig_type_array[sig_basename]=sig_type
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@ -276,75 +281,71 @@ primitive==1{primitive_line=primitive_line " " $0; next } # 20071217
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if( user_declarations!="") print user_declarations
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ttt[1]="constant"
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ttt[2]="variable"
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ttt[3]="signal"
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for(tt=1;tt<=3;tt++)
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for(i in arch_signal_dir)
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if(arch_signal_class[i]==ttt[tt])
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for(ii = 0; ii < arch_signal_n; ii++)
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{
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i = arch_signal_num[ii]
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## 04062002 don't add _vector if user defined type
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if(arch_sig_type_array[i] ~ /^(boolean|bit|real|std_logic|integer)$/)
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vector_type=arch_sig_type_array[i] "_vector ("
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else
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vector_type=arch_sig_type_array[i] " ("
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n=split(arch_index_array[i],tmp,",")
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hsort(tmp, n)
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if(n>1 || (arch_index_array[i] !~ /no_index/) ) #11092003 if not no_index treat as a bus
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{
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if(check(tmp,n))
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{
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if(arch_signal_dir[i] == " downto ")
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{
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## 04062002 don't add _vector if user defined type
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if(arch_sig_type_array[i] ~ /^(boolean|bit|real|std_logic|integer)$/)
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vector_type=arch_sig_type_array[i] "_vector ("
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else
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vector_type=arch_sig_type_array[i] " ("
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n=split(arch_index_array[i],tmp,",")
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hsort(tmp, n)
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if(n>1 || (arch_index_array[i] !~ /no_index/) ) #11092003 if not no_index treat as a bus
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{
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if(check(tmp,n))
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{
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if(arch_signal_dir[i] == " downto ")
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{
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arch_sig_name[entity_name, i "[" tmp[1] ":" tmp[n] "]"]=i
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printf "%s",arch_signal_class[i] " " i " : " vector_type tmp[1] " downto " tmp[n] ")" #04062002
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}
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else
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{
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arch_sig_name[entity_name, i "[" tmp[n] ":" tmp[1] "]"]=i
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printf "%s",arch_signal_class[i] " " i " : " vector_type tmp[n] " to " tmp[1] ")" #04062002
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}
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}
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else print "\n**** ERROR >>>> " i " non contigous bus ->" n, "|" arch_index_array[i] "|"
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}
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else
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{
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# we do not declare parametrized subranges as normally will result in redeclaration
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# of a port signal
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if( i ~ /\[.*\]/)
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{
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range = s_i(i)
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basename=s_b(i) # on exactly matching ranges
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arch_sig_name[entity_name, basename "[" range "]"]=i # used later in port maps to avoid specifying ranges
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if( !(basename in entity_ports) ) #09112003, eror corrected, basename instead of i in
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{ #arch_sig_name[entity_name,...
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if(range ~ /0:/)
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sub(/:/, " to ", range)
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else
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sub(/:/, " downto ", range)
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range= range ")"
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printf "%s",arch_signal_class[i] " " basename " : " vector_type range #04062002
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}
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else continue
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}
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else
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printf "%s",arch_signal_class[i] " " i " : " arch_sig_type_array[i]
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}
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if(arch_value_array[i] != "") { #08112004 add quotes on values
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if(tolower( arch_sig_type_array[i]) ~ /std_logic/ || # if not present
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tolower(arch_sig_type_array[i]) ~ /bit/ ) { # for verilog/VHDL compatiblity
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# if(tolower(arch_sig_type_array[i]) ~ /vector/) sep="\""
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if(n>1 || (arch_index_array[i] !~ /no_index/) ) sep="\""
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else sep = "'"
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if( arch_value_array[i] !~ sep)
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arch_value_array[i] = sep arch_value_array[i] sep
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}
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printf "%s"," := " arch_value_array[i]
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}
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printf " ;\n"
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arch_sig_name[entity_name, i "[" tmp[1] ":" tmp[n] "]"]=i
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printf "%s",arch_signal_class[i] " " i " : " vector_type tmp[1] " downto " tmp[n] ")" #04062002
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}
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else
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{
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arch_sig_name[entity_name, i "[" tmp[n] ":" tmp[1] "]"]=i
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printf "%s",arch_signal_class[i] " " i " : " vector_type tmp[n] " to " tmp[1] ")" #04062002
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}
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}
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else print "\n**** ERROR >>>> " i " non contigous bus ->" n, "|" arch_index_array[i] "|"
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}
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else
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{
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# we do not declare parametrized subranges as normally will result in redeclaration
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# of a port signal
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if( i ~ /\[.*\]/)
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{
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range = s_i(i)
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basename=s_b(i) # on exactly matching ranges
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arch_sig_name[entity_name, basename "[" range "]"]=i # used later in port maps to avoid specifying ranges
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if( !(basename in entity_ports) ) #09112003, eror corrected, basename instead of i in
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{ #arch_sig_name[entity_name,...
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if(range ~ /0:/)
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sub(/:/, " to ", range)
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else
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sub(/:/, " downto ", range)
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range= range ")"
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printf "%s",arch_signal_class[i] " " basename " : " vector_type range #04062002
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}
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else continue
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}
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else
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printf "%s",arch_signal_class[i] " " i " : " arch_sig_type_array[i]
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}
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if(arch_value_array[i] != "") { #08112004 add quotes on values
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if(tolower( arch_sig_type_array[i]) ~ /std_logic/ || # if not present
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tolower(arch_sig_type_array[i]) ~ /bit/ ) { # for verilog/VHDL compatiblity
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# if(tolower(arch_sig_type_array[i]) ~ /vector/) sep="\""
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if(n>1 || (arch_index_array[i] !~ /no_index/) ) sep="\""
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else sep = "'"
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if( arch_value_array[i] !~ sep)
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arch_value_array[i] = sep arch_value_array[i] sep
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}
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printf "%s"," := " arch_value_array[i]
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}
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printf " ;\n"
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}
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if(user_attributes!="") print user_attributes
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@ -366,7 +367,7 @@ primitive==1{primitive_line=primitive_line " " $0; next } # 20071217
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}
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($1==");" && port_map==1){
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nii=split(instance,ii,",")
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nii=split(instance,inst_arr,",")
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for(j=0;j<p;j++) {
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if(j>=g) { # do not split generics 06042005
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actual_port_mult=split(inst_actual_port[j],actual_port_array,",")
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@ -378,7 +379,7 @@ primitive==1{primitive_line=primitive_line " " $0; next } # 20071217
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ck2[j] = check2(actual_port_array,actual_port_mult)
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}
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for(i=1;i<=nii;i++) {
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print ii[i] " : " cell
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print inst_arr[i] " : " cell
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if(g>0)
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print "generic map ("
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else
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@ -400,7 +401,7 @@ primitive==1{primitive_line=primitive_line " " $0; next } # 20071217
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if(inst_formal_port_mult[j]<0) {
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parametrized_formal_range=1 # 20100408
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inst_formal_port_mult[j] = actual_port_mult
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inst_formal_up[j] = actual_port_mult -1 # 20100419 assume inst_formal_low=0 in case of parametrized vector port...
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inst_formal_up[j] = actual_port_mult -1 #assume inst_formal_low=0 in case of parametrized vector port...
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}
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a=((i-1)*inst_formal_port_mult[j]) % actual_port_mult+1
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@ -468,6 +469,7 @@ primitive==1{primitive_line=primitive_line " " $0; next } # 20071217
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}
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printf "\n);\n"
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}
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delete inst_arr
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port_map=0
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print_arch_definition=1
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no_print=1
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@ -163,9 +163,9 @@ proc netlist_test {} {
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global netlist_dir
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foreach {f t h} {
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rom8k.sch spice 1466291334
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greycnt.sch verilog 389394682
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greycnt.sch verilog 3391559642
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autozero_comp.sch spice 2011673313
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loading.sch vhdl 3704887277
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loading.sch vhdl 2601437773
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mos_power_ampli.sch spice 1186348644
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LCC_instances.sch spice 824427889
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simulate_ff.sch spice 1321596936
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@ -176,10 +176,11 @@ proc netlist_test {} {
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if {$t eq {verilog}} { set t v}
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set netlist_file $netlist_dir/[file rootname $f].$t
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## check netlist hashes, compare with gold hashes
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if { [xschem hash_file $netlist_file 1] == $h } {
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set netlist_hash [xschem hash_file $netlist_file 1]
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if { $netlist_hash == $h } {
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puts "$f netlist check OK"
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} else {
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puts "$f netlist check FAIL"
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puts "$f netlist check, expected hash: ${h}, calculated hash: ${netlist_hash}, FAIL"
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}
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}
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}
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@ -1,4 +1,4 @@
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v {xschem version=2.9.7 file_version=1.2}
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v {xschem version=3.0.0 file_version=1.2 }
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G {process
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begin
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A<='0';
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@ -76,11 +76,12 @@ wait for 10 ns;
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wait;
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end process;
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}
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K {}
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V {integer n = 0;
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initial begin
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$dumpfile("dumpfile.vcd");
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$dumpvars;
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$dumpvars(0, testbench);
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A=0;
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B=0;
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#1000;
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