Stefan Frederik 551bbcec0c Windows does not recognize XPending, fix typo for verilog_format`s port name: g instead of f		2021-11-26 13:16:52 +01:00
..
0_pcb_top.sch	allow tEDAx (flattened) netlisting of hierarchical schematics; added pcb/hierarchical_tedax example	2020-11-24 02:54:45 +01:00
74ls00-2.sym	preserve backslashes in instance name after doing an editprop(). get_tok_value() fix: do not eat "\" if called with with_quotes=1	2020-12-01 12:00:18 +01:00
74ls00.sym	allow new lines in net names (!)	2020-11-30 22:12:31 +01:00
7805.sym	allow tEDAx (flattened) netlisting of hierarchical schematics; added pcb/hierarchical_tedax example	2020-11-24 02:54:45 +01:00
bc817.sym	populating xschem git repo	2020-08-08 15:47:34 +02:00
hierarchical_tedax.sch	allow ! in net names, it got deleted after the parselabel rework.	2020-12-13 20:26:39 +01:00
hierarchical_tedax.sym	allow tEDAx (flattened) netlisting of hierarchical schematics; added pcb/hierarchical_tedax example	2020-11-24 02:54:45 +01:00
lm358.sym	removed weird names (spaces etc) in hierarchical_tedax schematic objects. that was used for testing the hiertEDAx export.	2020-11-24 19:55:45 +01:00
pcb_current_protection.sch	allow tEDAx (flattened) netlisting of hierarchical schematics; added pcb/hierarchical_tedax example	2020-11-24 02:54:45 +01:00
pcb_current_protection.sym	populating xschem git repo	2020-08-08 15:47:34 +02:00
pcb_current_protection_embed.sch	fix pcb_current_protection_embed.sch with up to date embedded symbols (previous had very old symbols with errors), fix pmos.sym (make pin names and verilog_format string consistent). All other schematics with embedded symbols updated with current library symbol. Some code in place for saving/restoring symbols in in-memory undo. This code is not compiled so does not affect xschem operation at all.	2021-11-25 04:00:01 +01:00
pcb_test1.sch	added menu option to load most recent file: ctrl-shift-o, fix menu entry "unhilight selected nets" (did unhilight all); removed a wire[].node clear in hash_wire() that caused broken connectivity. this data is cleared in delete_netlist_structs when needed.	2020-12-25 04:37:53 +01:00
pcb_test1.sym	populating xschem git repo	2020-08-08 15:47:34 +02:00
pcb_test1_embed.sch	fix pcb_current_protection_embed.sch with up to date embedded symbols (previous had very old symbols with errors), fix pmos.sym (make pin names and verilog_format string consistent). All other schematics with embedded symbols updated with current library symbol. Some code in place for saving/restoring symbols in in-memory undo. This code is not compiled so does not affect xschem operation at all.	2021-11-25 04:00:01 +01:00
pcb_test2.sch	preserve backslashes in instance name after doing an editprop(). get_tok_value() fix: do not eat "\" if called with with_quotes=1	2020-12-01 12:00:18 +01:00
pcb_voltage_protection.sch	populating xschem git repo	2020-08-08 15:47:34 +02:00
pcb_voltage_protection.sym	populating xschem git repo	2020-08-08 15:47:34 +02:00
pcb_voltage_protection_embed.sch	Windows does not recognize XPending, fix typo for verilog_format`s port name: g instead of f	2021-11-26 13:16:52 +01:00
reg.sch	removed weird names (spaces etc) in hierarchical_tedax schematic objects. that was used for testing the hiertEDAx export.	2020-11-24 19:55:45 +01:00
si2306.sym	populating xschem git repo	2020-08-08 15:47:34 +02:00
voltage_protection.sch	Added various procedures to select flat / hierarchical instances and re-route a terminal to a different net. reroute_inst -> change a pin connection, reroute_net -> change net updating all connected components. "xschem instances_to_net", "xschem instance_nodemap", "xschem instance_pin_coord" new query commands added. "xschem get expandlabel node" renamed to "xschem expandlabel node".	2020-11-26 03:46:55 +01:00
voltage_protection.sym	edit hierarchical_tedax.sch, different ways to instantiate more times same subschematic, as placed sheet or as symbol	2020-11-24 11:35:46 +01:00