stefan schippers
|
ecca0ba2be
|
better swap_windows() function (used when closing a window in multi-window(non-tabbed) interface, resolved_net() recognize global nodes. remove static data from record_global_node(), put in xctx. Remove dead code from translate() (@spice_get_voltage)
|
2023-11-12 13:01:11 +01:00 |
Stefan Schippers
|
8c29d0e812
|
fix error in capa-2.sym and missing check for null xctx->inst[].instname in get_pin_attr()
|
2023-11-11 20:03:20 +01:00 |
stefan schippers
|
b680f5da20
|
redraw screen if executing `xschem raw_read` (and raw file already loaded, thus unloading waves)
|
2023-10-29 12:54:55 +01:00 |
stefan schippers
|
94bccc08d9
|
do not duplicate empty strings as NULLs in hash tables
|
2023-10-09 12:49:11 +02:00 |
stefan schippers
|
9fee9610ab
|
vsource.sym and ammeter.sym: add "savecurrent=1|0|true|false" attribute do decide if a .save I(...) is to be printed in netlist. default is 1 for ammeter.sym and 0 for vsource.sym. Add "deltax deltay rot flip" optional parameters for xschem "copy_objects" command to make copy operation scriptable (lot more efficient than using clipboard)
|
2023-10-02 12:11:05 +02:00 |
stefan schippers
|
f8f7c4f230
|
updated moude_bindings.tcl with Paul`s new version, updated noconn.sym (do not use *_ignore attributes, put comments in netlist about NC net)
|
2023-06-30 09:11:04 +02:00 |
stefan schippers
|
245993f034
|
added attributes spice_ignore=short, verilog_ignore=short, .... that will transform the instance into a short in the current netlisting mode, shorting all pins to the same net. Works similarly as lvs_ignore=short, but does not need lvs_ignore global setting
|
2023-06-07 03:41:49 +02:00 |
stefan schippers
|
394db224d1
|
added global tcl variable `lvs_ignore` that can be used to enable instance or symbol attributes `lvs_ignore=open` or `lvs_ignore=short` while netlisting, added `test_lvs_ignore.sch` example
|
2023-06-06 15:22:45 +02:00 |
stefan schippers
|
ff216e8187
|
function reset_flags() set flags on symbols and instances; call reset_flags before rebuilding connectivity to update cached values; add short.sym component that can be used to short two nets together (and remove the short using *_ignore=true); instcheck(): do not proces instances that have *_ignore=true set.
|
2023-06-06 08:42:43 +02:00 |
stefan schippers
|
4f387f3bbe
|
disable displaying backannotation data if `b` cursor is hidden or `Simulation->Live annotation with b cursor` is disabled. Use resolved_net() in translate() when displaying @spice_get_voltage so it will work on sub block ports
|
2023-06-05 12:58:19 +02:00 |
stefan schippers
|
5085301cd7
|
add net_name=true in bus_tap.sym (so avoid setting it on instancs), add documentation for bus taps
|
2023-05-30 11:03:07 +02:00 |
stefan schippers
|
5043b14921
|
fix uninitialized wave_color due to regression after rainbow wave color enablement in double dc sweeps; more bus_tap.sym usage in examples; make bus_tap.sym work correctly for all netlist formats
|
2023-05-27 23:36:10 +02:00 |
stefan schippers
|
cf61c253c5
|
fix a bug in my_mstrcat if an empty string is appended; add resolved_net(n) function that returns the top-most hierarchy name of the net mapping to upper level port connections if any; add xschem resolved_net comand that returns the resolved_net of selected wire/label/pin; add @#n:resolved_net pattern in symbol texts that uses resolved_net
|
2023-05-27 11:20:49 +02:00 |
stefan schippers
|
d3b99d3a76
|
update n and p jfets, added pjfet simulation
|
2023-05-24 10:02:26 +02:00 |
stefan schippers
|
608a144dd1
|
fix tcl procedures using find_file to find a component: use find_file_first (return 1st match) , since find_file may return multiple matches; add njfet.sym, pjfet.sym and test_jfet.sch
|
2023-05-24 08:43:05 +02:00 |
Stefan Schippers
|
1774ff4e3a
|
allow @#n:pin_attr or @#pin_name:pin_attr in spice format string (print_spice_element), in addition to @#n (convergence to translate()
|
2023-05-22 21:50:14 +02:00 |
stefan schippers
|
0f1bbd24c8
|
devices/bus_tap.sym: remove format attr in symbol
|
2023-05-22 11:52:51 +02:00 |
stefan schippers
|
a4d5ddb63f
|
add examples/test_bus_tap.sch
|
2023-05-22 00:49:54 +02:00 |
stefan schippers
|
ea533bd9e3
|
added bus_tap.sym
|
2023-05-21 23:59:50 +02:00 |
stefan schippers
|
f110e817ef
|
ammeter.sym type set to "ammeter" instead of "probe", so will be greyed out if *_ignore attr is set
|
2023-05-11 00:47:59 +02:00 |
stefan schippers
|
339c523f0b
|
align symbol types, reducing number of different types (remove ngprobe, current_probe, differential_probe, raw_data_show --> probe
|
2023-05-10 17:46:16 +02:00 |
stefan schippers
|
0a4f942fb7
|
symbol_ignore=true attribute can be set on all symbol elements (text, lines, rectangles, arcs, polys, instances, nets) such that these marked elements are not displayed when symbol is instantiated.
|
2023-05-09 23:26:46 +02:00 |
stefan schippers
|
6b857f7b7d
|
switch_ngspice.sym: show (in very small font) @device_model (if given)
|
2023-04-30 10:37:45 +02:00 |
stefan schippers
|
fc18a69109
|
ind.sym artwork
|
2023-04-28 11:23:06 +02:00 |
stefan schippers
|
01bc76955e
|
fix simulator_commands_shown.sym (wrong and incompete quoting)
|
2023-02-13 19:15:35 +01:00 |
stefan schippers
|
e5227d6a31
|
rename top_subckt to lvs_netlist (more appropriate), better tcp interface (redirect stdout to socket in addition to command return value)
|
2023-02-09 11:30:27 +01:00 |
stefan schippers
|
af22c256b3
|
default to unlocked state (lock=false) at title 1st placement
|
2023-01-07 11:34:47 +01:00 |
stefan schippers
|
4c0d5023f5
|
allow 0 width lines (faster device dependent implementation) if user defined line width is set (to 0), add devices/title-3.sym
|
2023-01-07 11:28:28 +01:00 |
stefan schippers
|
19757ddd8a
|
add menu properties -> Edit header/License text, to allow inserting header or license metadata into the sch/sym file.
|
2023-01-02 03:04:35 +01:00 |
stefan schippers
|
609033e7ca
|
fix regression (not allowing to change text size)
|
2022-11-23 16:57:21 +01:00 |
Stefan Schippers
|
e7851d01db
|
"xschem set format <fmt_attribute>" will change netlisting format attribute instead of default "format" (or verilog_format or vhdl_format), however fallback to default netlisting rule attribute if not defined in symbol. add tcl function "from_eng <n>" to convert spice formatted numbers to floating point
|
2022-11-23 16:16:38 +01:00 |
Stefan Frederik
|
3d49ca63c9
|
avoid tcleval() of strings returned by translate2(), show currents of resistors and diodes when annotating.
|
2022-11-04 13:35:06 +01:00 |
Stefan Frederik
|
b98d836be3
|
devices/simulator_commands.sym: avoid recursive @param substitution in spice commands
|
2022-11-03 11:00:15 +01:00 |
Stefan Frederik
|
b36cd99e01
|
update simulator_commands.sym (missing close parenthesis at end, not causing any problem though)
|
2022-11-02 23:11:23 +01:00 |
Stefan Frederik
|
666b0ebd5b
|
show @path in title.sym
|
2022-11-01 13:26:22 +01:00 |
Stefan Frederik
|
b1f011f933
|
clean up testing @path in symbols
|
2022-11-01 13:17:51 +01:00 |
Stefan Frederik
|
b0a88325e7
|
"@path" will be expanded in symbols with the hierarchy path, so a fully qualified instance name is obtained with @path@name
|
2022-11-01 12:54:43 +01:00 |
Stefan Frederik
|
4c43e77818
|
eliminated hide=true attribute for backannotation current/voltage texts (will be hidden anyway if no sim data is loaded)
|
2022-10-24 17:28:39 +02:00 |
Stefan Frederik
|
18044abb3e
|
iopin.sym micro edit
|
2022-10-24 17:06:54 +02:00 |
Stefan Frederik
|
b8732f2321
|
ipin,iopin,opin reshaped to better show connection hotspot
|
2022-10-19 10:37:43 +02:00 |
Stefan Frederik
|
e14c8b9a11
|
wire labels: default name set to p1 instead of l1, so it will not clash with typical inductor names
|
2022-10-12 16:36:56 +02:00 |
Stefan Frederik
|
314acbabda
|
allow tabs and newlines in graph expressions in addition to spaces; updated example schematics
|
2022-09-23 02:18:51 +02:00 |
Stefan Frederik
|
3e2bc9f95e
|
added "Annotate operating point" into Simulation menu
|
2022-09-22 19:47:25 +02:00 |
Stefan Frederik
|
e61ef2eabf
|
fixed a potential parse error in edit_prop if list_tokens returns a non list due to malformed input. Added @spice_get_diff_voltage to get a voltage difference between 2 nodes.
|
2022-09-22 17:35:14 +02:00 |
Stefan Frederik
|
6f907b5430
|
updated test schematics to use new xschem annotate_op instead of ngspice::annotate
|
2022-09-21 18:38:53 +02:00 |
Stefan Frederik
|
9c89a08111
|
better backannotation info placement in net labels, fixes in translate() for @spice_get_voltage and @spice_get_current, fixes in ngspice_backannotate routines.
|
2022-09-21 17:24:16 +02:00 |
Stefan Frederik
|
931c1520e3
|
make op backannotation in schematic work also if raw file loaded at hierarchy level > 0
|
2022-09-21 13:58:01 +02:00 |
Stefan Frederik
|
b542186ebd
|
updated example schematics to new annotate / raw file loading methods
|
2022-09-20 18:25:31 +02:00 |
Stefan Frederik
|
8169196b35
|
bypass tcl for voltage and current backannotation in schematic from cursor b positon in graph
|
2022-09-20 03:12:46 +02:00 |
Stefan Frederik
|
7abceb3344
|
fix regression in ngspice::get_current, simplified voltage reporting in net label symbols
|
2022-09-20 00:12:27 +02:00 |