luke
/
xschem
mirror of https://github.com/StefanSchippers/xschem.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

"xschem set format <fmt_attribute>" will change netlisting format attribute instead of default "format" (or verilog_format or vhdl_format), however fallback to default netlisting rule attribute if not defined in symbol. add tcl function "from_eng <n>" to convert spice formatted numbers to floating point

This commit is contained in:
Stefan Schippers 2022-11-23 16:16:38 +01:00
parent 01df7876d7
commit e7851d01db
4 changed files with 55 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

32
src/token.c
View File

@ -697,11 +697,14 @@ static void print_vhdl_primitive(FILE *fd, int inst) /* netlist primitives, 200
my_strdup(514, &name, xctx->inst[inst].instname);
fmt_attr = xctx->format ? xctx->format : "vhdl_format";
if(!name) my_strdup(50, &name, get_tok_value(template, "name", 0));
/* allow format string override in instance */
my_strdup(1000, &format, get_tok_value(xctx->inst[inst].prop_ptr, fmt_attr, 2));
if(!format || !format[0])
if(!format && strcmp(fmt_attr, "vhdl_format"))
my_strdup(1630, &format, get_tok_value(xctx->inst[inst].prop_ptr, "vhdl_format", 2));
if(!format)
my_strdup(516, &format, get_tok_value((xctx->inst[inst].ptr + xctx->sym)->prop_ptr, fmt_attr, 2));
if(!format && strcmp(fmt_attr, "vhdl_format"))
my_strdup(1631, &format, get_tok_value((xctx->inst[inst].ptr + xctx->sym)->prop_ptr, "vhdl_format", 2));
if((name==NULL) || (format==NULL) ) {
my_free(1047, &template);
my_free(1048, &name);
@ -1126,9 +1129,13 @@ void print_vhdl_element(FILE *fd, int inst)
xRect *pinptr;
const char *fmt_attr = NULL;
Int_hashtable table = {NULL, 0};
const char *fmt;
fmt_attr = xctx->format ? xctx->format : "vhdl_format";
if(get_tok_value((xctx->inst[inst].ptr + xctx->sym)->prop_ptr, fmt_attr, 2)[0] != '\0') {
fmt = get_tok_value((xctx->inst[inst].ptr + xctx->sym)->prop_ptr, fmt_attr, 2);
if(!fmt[0] && strcmp(fmt_attr, "vhdl_format") )
fmt = get_tok_value((xctx->inst[inst].ptr + xctx->sym)->prop_ptr, "vhdl_format", 2);
if(fmt[0]) {
print_vhdl_primitive(fd, inst);
return;
}
@ -1508,6 +1515,8 @@ void print_spice_subckt_nodes(FILE *fd, int symbol)
fmt_attr = xctx->format ? xctx->format : "format";
my_strdup(103, &format1, get_tok_value(xctx->sym[symbol].prop_ptr, fmt_attr, 2));
if(!format1 && strcmp(fmt_attr, "format") )
my_strdup(1632, &format1, get_tok_value(xctx->sym[symbol].prop_ptr, "format", 2));
dbg(1, "print_spice_subckt(): format1=%s\n", format1);
if(format1 && strstr(format1, "tcleval(") == format1) {
tclres = tcl_hook2(&format1);
@ -1655,9 +1664,12 @@ int print_spice_element(FILE *fd, int inst)
/* allow format string override in instance */
fmt_attr = xctx->format ? xctx->format : "format";
my_strdup(470, &format, get_tok_value(xctx->inst[inst].prop_ptr, fmt_attr, 2));
if(!format || !format[0])
if(!format && strcmp(fmt_attr, "format") )
my_strdup(1633, &format, get_tok_value(xctx->inst[inst].prop_ptr, "format", 2));
if(!format)
my_strdup(486, &format, get_tok_value((xctx->inst[inst].ptr + xctx->sym)->prop_ptr, fmt_attr, 2));
if(!format && strcmp(fmt_attr, "format"))
my_strdup(1634, &format, get_tok_value((xctx->inst[inst].ptr + xctx->sym)->prop_ptr, "format", 2));
if ((name==NULL) || (format==NULL)) {
my_free(1015, &template);
my_free(1016, &format);
@ -2294,8 +2306,12 @@ static void print_verilog_primitive(FILE *fd, int inst) /* netlist switch level
fmt_attr = xctx->format ? xctx->format : "verilog_format";
/* allow format string override in instance */
my_strdup(1186, &format, get_tok_value(xctx->inst[inst].prop_ptr, fmt_attr, 2));
if(!format && strcmp(fmt_attr, "verilog_format") )
my_strdup(1635, &format, get_tok_value(xctx->inst[inst].prop_ptr, "verilog_format", 2));
if(!format || !format[0])
my_strdup(522, &format, get_tok_value((xctx->inst[inst].ptr + xctx->sym)->prop_ptr, fmt_attr, 2));
if(!format && strcmp(fmt_attr, "verilog_format"))
my_strdup(1636, &format, get_tok_value((xctx->inst[inst].ptr + xctx->sym)->prop_ptr, "verilog_format", 2));
if((name==NULL) || (format==NULL) ) {
my_free(1054, &template);
my_free(1055, &name);
@ -2492,9 +2508,13 @@ void print_verilog_element(FILE *fd, int inst)
int quote=0;
const char *fmt_attr = NULL;
Int_hashtable table = {NULL, 0};
const char *fmt;
fmt_attr = xctx->format ? xctx->format : "verilog_format";
if(get_tok_value((xctx->inst[inst].ptr + xctx->sym)->prop_ptr, fmt_attr, 2)[0] != '\0') {
fmt = get_tok_value((xctx->inst[inst].ptr + xctx->sym)->prop_ptr, fmt_attr, 2);
if(!fmt[0] && strcmp(fmt_attr, "verilog_format"))
fmt = get_tok_value((xctx->inst[inst].ptr + xctx->sym)->prop_ptr, "verilog_format", 2);
if(fmt[0]) {
print_verilog_primitive(fd, inst);
return;
}

5
src/verilog_netlist.c
View File

@ -133,6 +133,9 @@ void global_verilog_netlist(int global) /* netlister driver */
if( type && (strcmp(type,"timescale")==0 || strcmp(type,"verilog_preprocessor")==0) )
{
str_tmp = get_tok_value( (xctx->inst[i].ptr+ xctx->sym)->prop_ptr , fmt_attr, 2);
if(!str_tmp[0] && strcmp(fmt_attr, "verilog_format"))
str_tmp = get_tok_value( (xctx->inst[i].ptr+ xctx->sym)->prop_ptr, "verilog_format", 2);
my_strdup(106, &tmp_string, str_tmp);
fprintf(fd, "%s\n", str_tmp ? translate(i, tmp_string) : "(NULL)");
}
@ -468,6 +471,8 @@ void verilog_block_netlist(FILE *fd, int i)
if( type && ( strcmp(type,"timescale")==0 || strcmp(type,"verilog_preprocessor")==0) )
{
str_tmp = get_tok_value( (xctx->inst[j].ptr+ xctx->sym)->prop_ptr, fmt_attr, 2);
if(!str_tmp[0] && strcmp(fmt_attr, "verilog_format"))
str_tmp = get_tok_value( (xctx->inst[j].ptr+ xctx->sym)->prop_ptr, "verilog_format", 2);
my_strdup(545, &tmp_string, str_tmp);
fprintf(fd, "%s\n", str_tmp ? translate(j, tmp_string) : "(NULL)");
}

23
src/xschem.tcl
View File

@ -346,6 +346,29 @@ proc sframe {container} {
}
#### /Scrollable frame
## convert engineering form to number
proc from_eng {i} {
set str {}
scan $i "%g%s" n str
set str [string tolower $str]
if { [regexp {^meg} $str] } { set str {meg} } else {
set suffix [string index $str 0]
}
set mult [switch $suffix {
a { expr {1e-18}}
f { expr {1e-15}}
p { expr {1e-12}}
n { expr { 1e-9}}
u { expr {1e-6}}
m { expr {1e-3}}
k { expr {1e3}}
meg { expr {1e6}}
g { expr {1e9}}
t { expr {1e12}}
default { expr {1.0}}
}]
return [expr {$n * $mult}]
}
## convert number to engineering form
proc to_eng {i} {

1
xschem_library/devices/pmos4.sym
View File

@ -3,6 +3,7 @@ v {xschem version=3.1.0 file_version=1.2
G {}
K {type=pmos
format="@spiceprefix@name @pinlist @model w=@w l=@l @extra m=@m"
lvs_format="tcleval(@spiceprefix@name @pinlist @model w=@w l=@l @extra area=[expr [from_eng @w ] * [from_eng @l ] ] m=@m )"
template="name=M1 model=pmos w=5u l=0.18u del=0 m=1"
verilog_format="pmos #@del @name ( @@d , @@s , @@g );"}
V {}