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align symbol types, reducing number of different types (remove ngprobe, current_probe, differential_probe, raw_data_show --> probe

This commit is contained in:
stefan schippers 2023-05-10 17:46:16 +02:00
parent 4308b86744
commit 339c523f0b
8 changed files with 47 additions and 46 deletions
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79
src/draw.c
View File

@ -437,53 +437,54 @@ void draw_symbol(int what,int c, int n,int layer,short tmp_flip, short rot,
if(xctx->inst[n].ptr == -1) return;
if( layer == 0) {
if(
(
xctx->netlist_type == CAD_SPICE_NETLIST &&
char *type = xctx->sym[xctx->inst[n].ptr].type;
if( strcmp(type, "launcher") && strcmp(type, "logo") &&
strcmp(type, "probe") &&
strcmp(type, "architecture") && strcmp(type, "noconn")) {
if(
(
!strcmp(get_tok_value(xctx->inst[n].prop_ptr, "spice_ignore", 0), "true") ||
!strcmp(get_tok_value(xctx->sym[xctx->inst[n].ptr].prop_ptr, "spice_ignore", 0), "true")
)
) ||
(
xctx->netlist_type == CAD_VERILOG_NETLIST &&
xctx->netlist_type == CAD_SPICE_NETLIST &&
(
!strcmp(get_tok_value(xctx->inst[n].prop_ptr, "spice_ignore", 0), "true") ||
!strcmp(get_tok_value(xctx->sym[xctx->inst[n].ptr].prop_ptr, "spice_ignore", 0), "true")
)
) ||
(
!strcmp(get_tok_value(xctx->inst[n].prop_ptr, "verilog_ignore", 0), "true") ||
!strcmp(get_tok_value(xctx->sym[xctx->inst[n].ptr].prop_ptr, "verilog_ignore", 0), "true")
)
) ||
(
xctx->netlist_type == CAD_VHDL_NETLIST &&
xctx->netlist_type == CAD_VERILOG_NETLIST &&
(
!strcmp(get_tok_value(xctx->inst[n].prop_ptr, "verilog_ignore", 0), "true") ||
!strcmp(get_tok_value(xctx->sym[xctx->inst[n].ptr].prop_ptr, "verilog_ignore", 0), "true")
)
) ||
(
!strcmp(get_tok_value(xctx->inst[n].prop_ptr, "vhdl_ignore", 0), "true") ||
!strcmp(get_tok_value(xctx->sym[xctx->inst[n].ptr].prop_ptr, "vhdl_ignore", 0), "true")
)
) ||
(
xctx->netlist_type == CAD_TEDAX_NETLIST &&
xctx->netlist_type == CAD_VHDL_NETLIST &&
(
!strcmp(get_tok_value(xctx->inst[n].prop_ptr, "vhdl_ignore", 0), "true") ||
!strcmp(get_tok_value(xctx->sym[xctx->inst[n].ptr].prop_ptr, "vhdl_ignore", 0), "true")
)
) ||
(
!strcmp(get_tok_value(xctx->inst[n].prop_ptr, "tedax_ignore", 0), "true") ||
!strcmp(get_tok_value(xctx->sym[xctx->inst[n].ptr].prop_ptr, "tedax_ignore", 0), "true")
xctx->netlist_type == CAD_TEDAX_NETLIST &&
(
!strcmp(get_tok_value(xctx->inst[n].prop_ptr, "tedax_ignore", 0), "true") ||
!strcmp(get_tok_value(xctx->sym[xctx->inst[n].ptr].prop_ptr, "tedax_ignore", 0), "true")
)
)
)
) {
xctx->inst[n].flags |= 16; /* *_ignore=true */
} else {
xctx->inst[n].flags &= ~16;
) {
xctx->inst[n].flags |= 16; /* *_ignore=true */
} else {
xctx->inst[n].flags &= ~16;
}
}
}
if(xctx->inst[n].flags & 16) {
char *type = xctx->sym[xctx->inst[n].ptr].type;
if( strcmp(type, "launcher") && strcmp(type, "logo") && strcmp(type, "probe") &&
strcmp(type, "raw_data_show") && strcmp(type, "noconn")) {
c = GRIDLAYER;
what = NOW;
disabled = 1;
}
c = GRIDLAYER;
what = NOW;
disabled = 1;
}
if( (layer != PINLAYER && !xctx->enable_layer[layer]) ) return;
if(!has_x) return;

2
src/select.c
View File

@ -44,7 +44,7 @@ static void check_connected_wire(int stop_at_junction, int n)
for(init_inst_iterator(&ctx, x1, y1, x2, y2); (instptr = inst_iterator_next(&ctx)) ;) {
k = instptr->n;
type = (xctx->inst[k].ptr+ xctx->sym)->type;
if( type && (IS_LABEL_SH_OR_PIN(type) || !strcmp(type, "probe") || !strcmp(type, "ngprobe"))) {
if( type && (IS_LABEL_SH_OR_PIN(type) || !strcmp(type, "probe") )) {
double x0, y0;
xRect *rct;
rct=(xctx->inst[k].ptr+ xctx->sym)->rect[PINLAYER];

2
xschem_library/devices/ammeter.sym
View File

@ -1,7 +1,7 @@
v {xschem version=3.1.0 file_version=1.2
}
G {}
K {type=current_probe
K {type=probe
format="@name @pinlist 0
.save I( ?1 @name )"
template="name=Vmeas"}

2
xschem_library/devices/device_param_probe.sym
View File

@ -1,6 +1,6 @@
v {xschem version=3.0.0 file_version=1.2 }
G {}
K {type=raw_data_show
K {type=probe
vhdl_ignore=true
spice_ignore=false
verilog_ignore=true

2
xschem_library/devices/ngspice_get_expr.sym
View File

@ -1,6 +1,6 @@
v {xschem version=2.9.9 file_version=1.2 }
G {}
K {type=raw_data_show
K {type=probe
vhdl_ignore=true
spice_ignore=false
verilog_ignore=true

2
xschem_library/devices/ngspice_get_value.sym
View File

@ -1,6 +1,6 @@
v {xschem version=2.9.9 file_version=1.2 }
G {}
K {type=raw_data_show
K {type=probe
vhdl_ignore=true
spice_ignore=false
verilog_ignore=true

2
xschem_library/devices/ngspice_probe.sym
View File

@ -1,7 +1,7 @@
v {xschem version=3.1.0 file_version=1.2
}
G {}
K {type=ngprobe
K {type=probe
vhdl_ignore=true
spice_ignore=false
verilog_ignore=true

2
xschem_library/devices/spice_probe_vdiff.sym
View File

@ -1,7 +1,7 @@
v {xschem version=3.1.0 file_version=1.2
}
G {}
K {type=differential_probe
K {type=probe
format=".save v(@@p\\\\) v(@@m\\\\)"
template="name=p1"}
V {}