90d420eef3
Add initial MMCM feature and PIP support.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2020-10-08 17:44:42 -07:00
a2e275e44c
Add missing FREQ_BB active feature.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2020-10-01 17:31:50 -07:00
fbf4dd897d
Add or fix license header
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Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>
2020-05-26 07:33:12 -07:00
950d7534ec
Add licensing header to fuzzers' python scripts
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Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>
2020-05-26 07:33:12 -07:00
bc00250f90
Run make format.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2020-02-19 16:34:12 -08:00
6a50598cdc
Sort tilegrid_tdb.json for better debugging.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2020-02-19 16:34:12 -08:00
32833e6f93
Add diagnostic to find 005 instability.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2020-02-19 16:34:12 -08:00
9f839a7a08
Attempt to parallelize 074 for additional parts.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2020-02-19 16:34:11 -08:00
4efb540d96
Add stepdown feature to HCLK_IOI.
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- Also narrow HCLK_IOI tilegrid size to avoid coupling into [RL]IOI3.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-07-30 16:03:25 -07:00
f92fb52576
Merge branch 'master' into add_pll_interconnect_fuzzer
2019-07-08 11:22:49 -07:00
30648d554a
Complete initial PLL fuzzer.
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This solves for all unknown bits, but results in a large "IN_USE"
feature for apparently constant bits.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-07-03 13:18:58 -07:00
e096d9c172
005-tilegrid: Add HCLK_IOI base addresses calculation
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Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
2019-07-01 08:58:45 +02:00
9fb26b6915
005-tilegrid: calculate IOI base address
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Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
2019-06-25 11:32:32 +02:00
369362f8c8
005-tilegrid: add CFG_CENTER_MID tile base address calculation
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Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
2019-05-31 09:40:40 +02:00
66c7c4c3ab
Add fuzzers for HCLK_CMT tiles.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-03-15 18:43:21 -07:00
c2df5c97eb
Working complete HROW pip fuzzer.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-03-14 20:05:27 -07:00
5bebeb6c0d
Add CLK_BUFG to tilegrid.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-02-12 15:15:34 -08:00
00d9e1f314
Add CLK_HROW config fuzzer, and adjust tilegrid definition.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-02-08 14:23:39 -08:00
5e9cb60917
Add base addresses for CLK_HROW tiles. Word offset may be wrong.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-02-08 13:00:54 -08:00
b04598da26
Solve orphan INT columns in Kintex7.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-02-07 15:01:09 -08:00
bcd41b8d08
Add XADC INT and ICAP INT fuzzers to solve 2 of 4 missing INT columns.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-02-07 09:36:02 -08:00
ff3839f2b1
Remove some of the __future__.]
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-01-28 12:54:36 -08:00
bf8fd49ba4
Remove remaining usage of height, as words is the key.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-01-28 11:31:44 -08:00
32b9da0d97
Handle A7/K7/Z7 differences gracefully.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-01-27 22:30:53 -08:00
da08dfb99f
Add back INT propagation.
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All INT tiles are now populated for artix7 and the INT propagation
sanity checks output of fuzzers to ensure consistency.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-01-27 16:17:31 -08:00
40e7771fa5
Add HCLK back to tilegrid.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-01-27 08:20:48 -08:00
6424e5a701
Add DSP INT fuzzer.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-01-27 08:20:48 -08:00
0c94434db7
Add DSP back to tilegrid.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-01-27 08:20:48 -08:00
598c180a9f
Add INT tile fuzzers for CLB, IOB and BRAM tiles.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-01-27 08:20:48 -08:00
8cbbbfc4f8
Add INT tiles for IOB.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-01-27 08:20:48 -08:00
6a7acd4b23
Refactor all existing tiles to fuzzer approach.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-01-27 08:20:48 -08:00
8cbac3ee7a
Add monitor bits to tilegrid.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-01-27 08:20:48 -08:00
01e5aef7cc
005-tilegrid: format fix
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-01-14 13:00:55 +01:00
9c93f89662
005-tilegrid/add_tdb.py: Moved functions to util
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-01-14 12:58:24 +01:00
9e6c62cb4c
005-tilegrid: created a util script
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There is some shared code between add_tdb.py and generate_full.py. To
solve this I have added a util script containing shared code.
Moreover, in the case a block has to be overwritten, the add_tile_bits
function now checks if the two version of the block contain the same
information. If this does not happend the script fails.
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-01-14 12:58:24 +01:00
65f5ddb030
005-tilegrid/add_tdb.py: use floor divide
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-01-10 12:04:34 +01:00
b4ca31cd1e
005-tilegrid/add_tdb.py: added frame check
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This solves issue #481 . add_tdb.py now checks if all the bits in a same
tag have the same base address and, if that is the case, the first of
them is selected
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-01-10 11:43:53 +01:00
3738801ca3
005-tilegrid: removing unneeded comments
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-01-10 10:22:36 +01:00
bd32e51a38
005-tilegrid/add_tdb.py: change ps7 --> ps7_int
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-01-10 10:01:32 +01:00
7f6e6f1c8c
005-tilegrid/add_tdb.py: Changed frame and word params
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-01-09 19:07:40 +01:00
8bdf04a29d
005-tilegrid/add_tdb.py: Added ps7 tdb
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There is an hack to be fixed that selects only the first bit of the
tdb lines. It has to be corrected
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-01-09 18:14:23 +01:00
5acda63b46
xadc: tilegrid support
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Signed-off-by: John McMaster <johndmcmaster@gmail.com>
2018-12-29 17:07:18 +01:00
dde83ebadb
tilegrid: pll/mmcm entire major address until resolved
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Signed-off-by: John McMaster <johndmcmaster@gmail.com>
2018-12-18 17:12:13 -08:00
3b1b587fcf
tilegrid pll: basic support
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Signed-off-by: John McMaster <johndmcmaster@gmail.com>
2018-12-18 16:06:53 -08:00
b84d9a2535
tilegrid: basic mmcm support
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Signed-off-by: John McMaster <johndmcmaster@gmail.com>
2018-12-18 15:42:23 -08:00
b501c10fa2
tilegrid iob: generate addresses automatically
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Signed-off-by: John McMaster <johndmcmaster@gmail.com>
2018-12-17 16:38:25 -08:00
Keith Rothman
Tomasz Michalak
Alessandro Comodi
John McMaster