Add CLK_BUFG to tilegrid.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman 2019-02-12 10:54:09 -08:00
parent f29fe77ea9
commit 5bebeb6c0d
5 changed files with 93 additions and 0 deletions

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@ -14,6 +14,7 @@ TILEGRID_TDB_DEPENDENCIES += fifo_int/build/segbits_tilegrid.tdb
TILEGRID_TDB_DEPENDENCIES += cfg_int/build/segbits_tilegrid.tdb
TILEGRID_TDB_DEPENDENCIES += monitor_int/build/segbits_tilegrid.tdb
TILEGRID_TDB_DEPENDENCIES += clk_hrow/build/segbits_tilegrid.tdb
TILEGRID_TDB_DEPENDENCIES += clk_bufg/build/segbits_tilegrid.tdb
GENERATE_FULL_ARGS=
ifeq (${XRAY_DATABASE}, zynq7)
@ -100,6 +101,9 @@ orphan_int_column/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
clk_hrow/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
cd clk_hrow && $(MAKE)
clk_bufg/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
cd clk_bufg && $(MAKE)
build/tilegrid_tdb.json: add_tdb.py $(TILEGRID_TDB_DEPENDENCIES)
python3 add_tdb.py \
--fn-in build/basicdb/tilegrid.json \
@ -134,6 +138,7 @@ clean:
cd cfg_int && $(MAKE) clean
cd orphan_int_column && $(MAKE) clean
cd clk_hrow && $(MAKE) clean
cd clk_bufg && $(MAKE) clean
.PHONY: database pushdb clean run

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@ -85,6 +85,7 @@ def run(fn_in, fn_out, verbose=False):
("clb/build/segbits_tilegrid.tdb", 36, 2),
("dsp/build/segbits_tilegrid.tdb", 28, 10),
("clk_hrow/build/segbits_tilegrid.tdb", 30, 7),
("clk_bufg/build/segbits_tilegrid.tdb", 30, 8),
("clb_int/build/segbits_tilegrid.tdb", int_frames, int_words),
("iob_int/build/segbits_tilegrid.tdb", int_frames, int_words),
("bram_int/build/segbits_tilegrid.tdb", int_frames, int_words),

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@ -0,0 +1,4 @@
N ?= 5
GENERATE_ARGS?="--oneval 1 --design params.csv --dword 0 --dframe 1B"
include ../fuzzaddr/common.mk

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@ -0,0 +1,21 @@
source "$::env(XRAY_DIR)/utils/utils.tcl"
proc run {} {
create_project -force -part $::env(XRAY_PART) design design
read_verilog top.v
synth_design -top top
#set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
place_design
route_design
write_checkpoint -force design.dcp
write_bitstream -force design.bit
}
run

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@ -0,0 +1,62 @@
import os
import random
random.seed(int(os.getenv("SEED"), 16))
from prjxray import util
from prjxray.db import Database
def gen_sites():
db = Database(util.get_db_root())
grid = db.grid()
for tile_name in grid.tiles():
loc = grid.loc_of_tilename(tile_name)
gridinfo = grid.gridinfo_at_loc(loc)
sites = []
for site, site_type in gridinfo.sites.items():
if site_type == 'BUFGCTRL':
sites.append(site)
if sites:
yield tile_name, sorted(sites)
def write_params(params):
pinstr = 'tile,val,site\n'
for tile, (site, val) in sorted(params.items()):
pinstr += '%s,%s,%s\n' % (tile, val, site)
open('params.csv', 'w').write(pinstr)
def run():
print('''
module top();
''')
params = {}
sites = list(gen_sites())
for (tile_name, sites), isone in zip(sites,
util.gen_fuzz_states(len(sites))):
site_name = sites[0]
params[tile_name] = (site_name, isone)
print(
'''
(* KEEP, DONT_TOUCH, LOC = "{site}" *)
BUFGCTRL #(
.INIT_OUT({isone})
) buf_{site} (
.CE0(1),
.S0(1)
);
'''.format(
site=site_name,
isone=isone,
))
print("endmodule")
write_params(params)
if __name__ == '__main__':
run()