mirror of https://github.com/openXC7/prjxray.git
005-tilegrid: created a util script
There is some shared code between add_tdb.py and generate_full.py. To solve this I have added a util script containing shared code. Moreover, in the case a block has to be overwritten, the add_tile_bits function now checks if the two version of the block contain the same information. If this does not happend the script fails. Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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@ -3,44 +3,7 @@
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from prjxray import util
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import json
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import os
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# Copied from generate_full.py
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def add_tile_bits(tile_db, baseaddr, offset, frames, words, height=None):
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'''
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Record data structure geometry for the given tile baseaddr
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For most tiles there is only one baseaddr, but some like BRAM have multiple
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Notes on multiple block types:
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https://github.com/SymbiFlow/prjxray/issues/145
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'''
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bits = tile_db['bits']
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block_type = util.addr2btype(baseaddr)
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assert 0 <= offset <= 100, offset
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assert 1 <= words <= 101
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assert offset + words <= 101, (
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tile_db, offset + words, offset, words, block_type)
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assert block_type not in bits
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block = bits.setdefault(block_type, {})
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# FDRI address
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block["baseaddr"] = '0x%08X' % baseaddr
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# Number of frames this entry is sretched across
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# that is the following FDRI addresses are used: range(baseaddr, baseaddr + frames)
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block["frames"] = frames
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# Index of first word used within each frame
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block["offset"] = offset
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# related to words...
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# deprecated field? Don't worry about for now
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# DSP has some differences between height and words
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block["words"] = words
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if height is None:
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height = words
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block["height"] = height
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import util as localutil
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def parse_addr(line):
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@ -129,7 +92,7 @@ def run(fn_in, fn_out, verbose=False):
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bitsj = tilej['bits']
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bt = util.addr2btype(frame)
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verbose and print("Add %s %08X_%03u" % (tile, frame, wordidx))
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add_tile_bits(tilej, frame, wordidx, frames, words)
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localutil.add_tile_bits(tile, tilej, frame, wordidx, frames, words)
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# Save
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json.dump(
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@ -12,6 +12,7 @@ A post processing step verifies that two tiles don't reference the same bitstrea
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from generate import load_tiles
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from prjxray import util
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import util as localutil
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def nolr(tile_type):
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@ -494,42 +495,6 @@ def seg_base_addr_up_INT(database, segments, tiles_by_grid, verbose=False):
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wordbase)
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def add_tile_bits(tile_db, baseaddr, offset, frames, words, height=None):
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'''
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Record data structure geometry for the given tile baseaddr
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For most tiles there is only one baseaddr, but some like BRAM have multiple
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Notes on multiple block types:
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https://github.com/SymbiFlow/prjxray/issues/145
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'''
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bits = tile_db['bits']
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block_type = util.addr2btype(baseaddr)
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assert 0 <= offset <= 100, offset
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assert 1 <= words <= 101
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assert offset + words <= 101, (
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tile_db, offset + words, offset, words, block_type)
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#assert block_type not in bits:
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block = bits.setdefault(block_type, {})
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# FDRI address
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block["baseaddr"] = '0x%08X' % baseaddr
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# Number of frames this entry is sretched across
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# that is the following FDRI addresses are used: range(baseaddr, baseaddr + frames)
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block["frames"] = frames
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# Index of first word used within each frame
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block["offset"] = offset
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# related to words...
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# deprecated field? Don't worry about for now
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# DSP has some differences between height and words
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block["words"] = words
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if height is None:
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height = words
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block["height"] = height
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def db_add_bits(database, segments):
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'''Transfer segment data into tiles'''
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for segment_name in segments.keys():
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@ -597,9 +562,9 @@ def db_add_bits(database, segments):
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if frames:
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# if we have a width, we should have a height
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assert frames and words
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add_tile_bits(
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database[tile_name], baseaddr, offset, frames, words,
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height)
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localutil.add_tile_bits(
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tile_name, database[tile_name], baseaddr, offset,
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frames, words, height)
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def db_add_segments(database, segments):
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@ -0,0 +1,62 @@
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#!/usr/bin/env python3
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from prjxray import util
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'''
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Local utils script to hold shared code of the 005-tilegrid fuzzer scripts
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'''
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def add_tile_bits(
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tile_name,
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tile_db,
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baseaddr,
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offset,
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frames,
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words,
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height=None,
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verbose=False):
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'''
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Record data structure geometry for the given tile baseaddr
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For most tiles there is only one baseaddr, but some like BRAM have multiple
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Notes on multiple block types:
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https://github.com/SymbiFlow/prjxray/issues/145
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'''
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bits = tile_db['bits']
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block_type = util.addr2btype(baseaddr)
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assert offset <= 100, (tile_name, offset)
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# Few rare cases at X=0 for double width tiles split in half => small negative offset
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assert offset >= 0 or "IOB" in tile_name, (tile_name, offset)
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assert 1 <= words <= 101
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assert offset + words <= 101, (
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tile_name, offset + words, offset, words, block_type)
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baseaddr_str = '0x%08X' % baseaddr
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block = bits.get(block_type, None)
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if block is not None:
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verbose and print(
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"%s: existing defintion for %s" % (tile_name, block_type))
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assert block["baseaddr"] == baseaddr_str
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assert block["frames"] == frames
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assert block["offset"] == offset, "%s; orig offset %s, new %s" % (
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tile_name, block["offset"], offset)
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assert block["words"] == words
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block = bits.setdefault(block_type, {})
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# FDRI address
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block["baseaddr"] = baseaddr_str
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# Number of frames this entry is sretched across
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# that is the following FDRI addresses are used: range(baseaddr, baseaddr + frames)
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block["frames"] = frames
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# Index of first word used within each frame
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block["offset"] = offset
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# related to words...
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# deprecated field? Don't worry about for now
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# DSP has some differences between height and words
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block["words"] = words
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if height is None:
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height = words
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block["height"] = height
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