mirror of https://github.com/openXC7/prjxray.git
Add DSP INT fuzzer.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman
parent
0c94434db7
commit
6424e5a701
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@ -12,6 +12,7 @@ TILEGRID_TDB_DEPENDENCIES += bram_int/build/segbits_tilegrid.tdb
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TILEGRID_TDB_DEPENDENCIES += clb/build/segbits_tilegrid.tdb
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TILEGRID_TDB_DEPENDENCIES += clb_int/build/segbits_tilegrid.tdb
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TILEGRID_TDB_DEPENDENCIES += dsp/build/segbits_tilegrid.tdb
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TILEGRID_TDB_DEPENDENCIES += dsp_int/build/segbits_tilegrid.tdb
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GENERATE_FULL_ARGS=
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ifeq (${XRAY_DATABASE}, zynq7)
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@ -69,6 +70,9 @@ bram_int/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
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dsp/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
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cd dsp && $(MAKE)
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dsp_int/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
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cd dsp_int && $(MAKE)
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build/tilegrid_tdb.json: add_tdb.py $(TILEGRID_TDB_DEPENDENCIES)
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python3 add_tdb.py \
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--fn-in build/basicdb/tilegrid.json \
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@ -97,6 +101,7 @@ clean:
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cd bram_block && $(MAKE) clean
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cd bram_int && $(MAKE) clean
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cd dsp && $(MAKE) clean
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cd dsp_int && $(MAKE) clean
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cd monitor && $(MAKE) clean
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.PHONY: database pushdb clean run
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@ -67,6 +67,7 @@ def run(fn_in, fn_out, verbose=False):
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("clb_int/build/segbits_tilegrid.tdb", int_frames, int_words),
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("iob_int/build/segbits_tilegrid.tdb", int_frames, int_words),
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("bram_int/build/segbits_tilegrid.tdb", int_frames, int_words),
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("dsp_int/build/segbits_tilegrid.tdb", int_frames, int_words),
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]
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for (tdb_fn, frames, words) in tdb_fns:
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@ -0,0 +1,4 @@
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N ?= 10
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GENERATE_ARGS?="--oneval 0 --design params.csv --dword 1 --dframe 15"
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include ../fuzzaddr/common.mk
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@ -0,0 +1,21 @@
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source "$::env(XRAY_DIR)/utils/utils.tcl"
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proc run {} {
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property IS_ENABLED 0 [get_drc_checks {DSPS-3}]
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set_property IS_ENABLED 0 [get_drc_checks {DSPS-5}]
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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}
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run
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@ -0,0 +1,160 @@
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import os
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import random
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import itertools
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random.seed(int(os.getenv("SEED"), 16))
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from prjxray import util
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from prjxray.db import Database
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def gen_dsps():
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db = Database(util.get_db_root())
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grid = db.grid()
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for tile_name in sorted(grid.tiles()):
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loc = grid.loc_of_tilename(tile_name)
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gridinfo = grid.gridinfo_at_loc(loc)
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sites = []
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for site_name, site_type in gridinfo.sites.items():
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if site_type in ['DSP48E1']:
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sites.append(site_name)
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sites.sort()
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if len(sites) == 0:
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continue
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if gridinfo.tile_type[-1] == 'L':
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int_grid_x = loc.grid_x + 2
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int_tile_type = 'INT_L'
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else:
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int_grid_x = loc.grid_x - 2
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int_tile_type = 'INT_R'
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int_tile_locs = [
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(int_grid_x, loc.grid_y),
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(int_grid_x, loc.grid_y - 1),
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(int_grid_x, loc.grid_y - 2),
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(int_grid_x, loc.grid_y - 3),
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(int_grid_x, loc.grid_y - 4),
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]
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int_tiles = []
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for int_tile_loc in int_tile_locs:
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int_gridinfo = grid.gridinfo_at_loc(int_tile_loc)
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assert int_gridinfo.tile_type == int_tile_type, (
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int_gridinfo.tile_type, int_tile_type)
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int_tiles.append(grid.tilename_at_loc(int_tile_loc))
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yield tile_name, sites, int_tiles
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def write_params(params):
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pinstr = 'tile,val\n'
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for tile, (val, ) in sorted(params.items()):
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pinstr += '%s,%s\n' % (tile, val)
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open('params.csv', 'w').write(pinstr)
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def run():
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print('''
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module top();
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''')
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params = {}
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sites = list(gen_dsps())
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fuzz_iter = iter(util.gen_fuzz_states(len(sites) * 5))
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for tile_name, dsp_sites, int_tiles in sites:
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# Each DSP tile has 5 INT tiles.
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# The following feature is used to toggle a one PIP in each INT tile
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#
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# For a DSP, there are the following INT tiles and the feature
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# to toggle
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#
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# INT_L_X34Y89/INT_L.GFAN1->>IMUX_L30 :: D1.C36 = 0
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# INT_L_X34Y89/INT_L.GFAN1->>IMUX_L28 :: D1.CARRYINSEL1 = toggle
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#
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# INT_L_X34Y88/INT_L.GFAN1->>IMUX_L30 :: D0.CARRYINSEL0 = toggle
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#
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# INT_L_X34Y87/INT_L.GFAN1->>IMUX_L5 :: D1.A29 = 0
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# INT_L_X34Y87/INT_L.GFAN1->>IMUX_L14 :: D1.B8 = toggle
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#
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# INT_L_X34Y86/INT_L.GFAN1->>IMUX_L30 :: D1.B4 = 0
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# INT_L_X34Y86/INT_L.GFAN1->>IMUX_L28 :: D1.B6 = toggle
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#
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# INT_L_X34Y85/INT_L.GFAN1->>IMUX_L30 :: Dark Green :: D1.C20 = 0
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# INT_L_X34Y85/INT_L.GFAN1->>IMUX_L28 :: Color 10 :: D1.B2 = toggle
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(d1_carryinsel1, d0_carryinsel0, d1_b8, d1_b6, d1_b2
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) = itertools.islice(fuzz_iter, 5)
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params[int_tiles[0]] = (d1_carryinsel1, )
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params[int_tiles[1]] = (d0_carryinsel0, )
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params[int_tiles[2]] = (d1_b8, )
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params[int_tiles[3]] = (d1_b6, )
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params[int_tiles[4]] = (d1_b2, )
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print(
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'''
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wire [6:0] {dsp_site0}_opmode;
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wire [2:0] {dsp_site0}_carryinsel;
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wire [29:0] {dsp_site1}_a;
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wire [17:0] {dsp_site1}_b;
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wire [47:0] {dsp_site1}_c;
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wire [6:0] {dsp_site1}_opmode;
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wire [2:0] {dsp_site1}_carryinsel;
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// INT 0
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assign {dsp_site1}_c[36] = 0;
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assign {dsp_site1}_carryinsel[1] = {d1_carryinsel1};
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// INT 1
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assign {dsp_site0}_carryinsel[0] = {d0_carryinsel0};
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// INT 2
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assign {dsp_site1}_a[29] = 0;
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assign {dsp_site1}_b[8] = {d1_b8};
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// INT 3
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assign {dsp_site1}_b[4] = 0;
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assign {dsp_site1}_b[6] = {d1_b6};
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// INT 4
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assign {dsp_site1}_c[20] = 0;
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assign {dsp_site1}_b[2] = {d1_b2};
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(* KEEP, DONT_TOUCH, LOC = "{dsp_site0}" *)
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DSP48E1 #(
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.OPMODEREG(0),
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.CREG(0)
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) dsp_{dsp_site0} (
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.OPMODE({dsp_site0}_opmode),
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.CARRYINSEL({dsp_site0}_carryinsel)
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);
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(* KEEP, DONT_TOUCH, LOC = "{dsp_site1}" *)
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DSP48E1 #(
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.OPMODEREG(0),
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.CREG(0)
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) dsp_{dsp_site1} (
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.OPMODE({dsp_site1}_opmode),
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.CARRYINSEL({dsp_site1}_carryinsel),
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.A({dsp_site1}_a),
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.B({dsp_site1}_b),
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.C({dsp_site1}_c)
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);
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'''.format(
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dsp_site0=dsp_sites[0],
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dsp_site1=dsp_sites[1],
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d1_carryinsel1=d1_carryinsel1,
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d0_carryinsel0=d0_carryinsel0,
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d1_b8=d1_b8,
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d1_b6=d1_b6,
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d1_b2=d1_b2))
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print("endmodule")
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write_params(params)
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if __name__ == '__main__':
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run()
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@ -1,3 +1,3 @@
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N ?= 35
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GENERATE_ARGS?="--oneval 0 --design params.csv --dframe 15 --dword 1"
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GENERATE_ARGS?="--oneval 0 --design params.csv --dframe 14 --dword 1"
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include ../fuzzaddr/common.mk
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