mirror of https://github.com/openXC7/prjxray.git
Add back INT propagation.
All INT tiles are now populated for artix7 and the INT propagation sanity checks output of fuzzers to ensure consistency. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman
parent
3a4fc5eedc
commit
da08dfb99f
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@ -13,6 +13,7 @@ TILEGRID_TDB_DEPENDENCIES += clb/build/segbits_tilegrid.tdb
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TILEGRID_TDB_DEPENDENCIES += clb_int/build/segbits_tilegrid.tdb
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TILEGRID_TDB_DEPENDENCIES += dsp/build/segbits_tilegrid.tdb
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TILEGRID_TDB_DEPENDENCIES += dsp_int/build/segbits_tilegrid.tdb
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TILEGRID_TDB_DEPENDENCIES += fifo_int/build/segbits_tilegrid.tdb
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GENERATE_FULL_ARGS=
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ifeq (${XRAY_DATABASE}, zynq7)
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@ -73,6 +74,9 @@ dsp/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
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dsp_int/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
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cd dsp_int && $(MAKE)
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fifo_int/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
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cd fifo_int && $(MAKE)
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build/tilegrid_tdb.json: add_tdb.py $(TILEGRID_TDB_DEPENDENCIES)
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python3 add_tdb.py \
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--fn-in build/basicdb/tilegrid.json \
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@ -102,6 +106,7 @@ clean:
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cd bram_int && $(MAKE) clean
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cd dsp && $(MAKE) clean
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cd dsp_int && $(MAKE) clean
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cd fifo_int && $(MAKE) clean
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cd monitor && $(MAKE) clean
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.PHONY: database pushdb clean run
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@ -66,6 +66,7 @@ def run(fn_in, fn_out, verbose=False):
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("iob_int/build/segbits_tilegrid.tdb", int_frames, int_words),
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("bram_int/build/segbits_tilegrid.tdb", int_frames, int_words),
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("dsp_int/build/segbits_tilegrid.tdb", int_frames, int_words),
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("fifo_int/build/segbits_tilegrid.tdb", int_frames, int_words),
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]
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for (tdb_fn, frames, words) in tdb_fns:
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@ -1,4 +1,4 @@
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N ?= 16
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GENERATE_ARGS?="--oneval 0 --design params.csv --dword 1 --dframe 15"
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GENERATE_ARGS?="--oneval 0 --design params.csv --dword 0 --dframe 15"
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include ../fuzzaddr/common.mk
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@ -23,15 +23,14 @@ def gen_fifos():
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int_tile_type = 'INT_R'
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int_tile_locs = [
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(int_grid_x, loc.grid_y+idx-5) for idx in range(12)
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]
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(int_grid_x, loc.grid_y + idx - 5) for idx in range(12)
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]
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int_tiles = []
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for int_tile_loc in int_tile_locs:
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int_gridinfo = grid.gridinfo_at_loc(int_tile_loc)
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assert int_gridinfo.tile_type == int_tile_type, (
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int_tile_loc,
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int_gridinfo.tile_type, int_tile_type)
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int_tile_loc, int_gridinfo.tile_type, int_tile_type)
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int_tiles.append(grid.tilename_at_loc(int_tile_loc))
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@ -68,11 +67,11 @@ module top();
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#
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# INT[idx].IMUX_L40 = IN.D{idx}[1]
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# INT[idx].IMUX_L42 = IN.D{idx}[3]
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CHANNEL = [0, 1, 2, 3, 4, 5, 5, 6, 6, 7, 8, 9]
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CHANNEL = [0, 1, 2, 3, 4, 5, 5, 6, 6, 7, 8, 9]
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HOLD_BIT_0 = [1, 1, 1, 1, 1, 1, 5, 5, 1, 1, 1, 1]
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TOGGLE_BIT = [3, 3, 3, 3, 3, 3, 7, 7, 3, 3, 3, 3]
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# 0 1 2 3 4 5 6 7 8 9
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WIDTH = [4, 4, 4, 4, 4, 8, 8, 4, 4, 4]
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WIDTH = [4, 4, 4, 4, 4, 8, 8, 4, 4, 4]
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bits_set = set()
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@ -81,29 +80,33 @@ module top();
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bits_set.add((CHANNEL[idx], TOGGLE_BIT[idx]))
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assigns.append(' // {}'.format(int_tile))
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assigns.append(' assign {site}_in_d{channel}[{bit}] = 0;'.format(
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site=site,
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channel=CHANNEL[idx],
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bit=HOLD_BIT_0[idx],
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assigns.append(
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' assign {site}_in_d{channel}[{bit}] = 0;'.format(
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site=site,
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channel=CHANNEL[idx],
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bit=HOLD_BIT_0[idx],
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))
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assigns.append(' assign {site}_in_d{channel}[{bit}] = {toggle_bit};'.format(
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site=site,
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channel=CHANNEL[idx],
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bit=TOGGLE_BIT[idx],
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toggle_bit=bit,
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assigns.append(
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' assign {site}_in_d{channel}[{bit}] = {toggle_bit};'
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.format(
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site=site,
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channel=CHANNEL[idx],
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bit=TOGGLE_BIT[idx],
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toggle_bit=bit,
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))
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params[int_tile] = (bit,)
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params[int_tile] = (bit, )
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assigns.append('')
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for channel, width in enumerate(WIDTH):
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for bit in range(width):
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if (channel, bit) not in bits_set:
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assigns.append(' assign {site}_in_d{channel}[{bit}] = 1;'.format(
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site=site,
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channel=channel,
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bit=bit,
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assigns.append(
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' assign {site}_in_d{channel}[{bit}] = 1;'.
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format(
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site=site,
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channel=channel,
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bit=bit,
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))
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print(
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@ -1,6 +1,6 @@
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#!/usr/bin/env python3
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from __future__ import print_function
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import sys, json
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import json
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from utils import xjson
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'''
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Historically we grouped data into "segments"
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@ -12,7 +12,6 @@ Decoding was then shifted to instead describe how each title is encoded
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A post processing step verifies that two tiles don't reference the same bitstream area
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'''
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from generate import load_tiles
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import util as localutil
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@ -60,109 +59,10 @@ def make_tiles_by_grid(database):
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return tiles_by_grid
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def add_int_bits(database, tile, baseaddr, offset):
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"""
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Add INT bits for given tile.
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"""
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if database[tile]['type'] not in ["INT_L", "INT_R"]:
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return
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localutil.add_tile_bits(
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tile, database[tile], baseaddr, offset, frames=28, words=2, height=2)
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def add_adjacent_int_tiles(database, tiles_by_grid, verbose=False):
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'''
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Attaches INT tiles adjacent to tiles.
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'''
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def add_int_tile(inttile, parent_tile):
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if not database[parent_tile]['bits']:
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return
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grid_x = database[inttile]["grid_x"]
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grid_y = database[inttile]["grid_y"]
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framebase = int(
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database[parent_tile]['bits']['CLB_IO_CLK']['baseaddr'], 0)
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parent_wordbase = database[parent_tile]['bits']['CLB_IO_CLK']['offset']
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for dst_tile, wordbase in localutil.propagate_up_INT(
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grid_x, grid_y, database, tiles_by_grid, parent_wordbase):
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dst_x = dst_tile['grid_x']
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dst_y = dst_tile['grid_y']
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add_int_bits(
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database, tiles_by_grid[(dst_x, dst_y)], framebase, wordbase)
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verbose and print('')
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for tile_name, tile_data in database.items():
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tile_type = tile_data["type"]
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grid_x = tile_data["grid_x"]
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grid_y = tile_data["grid_y"]
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def process_clb():
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if tile_type in ["CLBLL_L", "CLBLM_L"]:
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int_tile_name = tiles_by_grid[(grid_x + 1, grid_y)]
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else:
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int_tile_name = tiles_by_grid[(grid_x - 1, grid_y)]
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add_int_tile(int_tile_name, tile_name)
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def process_iob():
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if tile_type.startswith('LIOB'):
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# Two INT_L's
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#add_int_tile(tiles_by_grid[(grid_x + 4, grid_y)], tile_name)
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#add_int_tile(tiles_by_grid[(grid_x + 4, grid_y - 1)], tile_name)
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pass
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else:
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# Two INT_R's
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#add_int_tile(tiles_by_grid[(grid_x - 4, grid_y)], tile_name)
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#add_int_tile(tiles_by_grid[(grid_x - 4, grid_y - 1)], tile_name)
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pass
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def process_iob_sing():
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if tile_type.startswith('LIOB'):
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add_int_tile(tiles_by_grid[(grid_x + 4, grid_y)], tile_name)
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else:
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add_int_tile(tiles_by_grid[(grid_x - 4, grid_y)], tile_name)
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def process_bram_dsp():
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for k in range(5):
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if tile_type in ["BRAM_L", "DSP_L"]:
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int_tile_name = tiles_by_grid[(grid_x + 2, grid_y - k)]
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elif tile_type in ["BRAM_R", "DSP_R"]:
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int_tile_name = tiles_by_grid[(grid_x - 2, grid_y - k)]
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else:
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assert 0
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add_int_tile(int_tile_name, tile_name)
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def process_default():
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verbose and nolr(tile_type) not in (
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'VBRK', 'INT', 'NULL') and print(
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'make_segment: drop %s' % (tile_type, ))
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pass
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{
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"CLBLL": process_clb,
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"CLBLM": process_clb,
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"HCLK": lambda: None,
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"BRAM": lambda: None,
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"DSP": lambda: None,
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"RIOB33": process_iob,
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"LIOB33": process_iob,
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"RIOB33_SING": process_iob_sing,
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"LIOB33_SING": process_iob_sing,
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}.get(nolr(tile_type), process_default)()
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def seg_base_addr_lr_INT(database, tiles_by_grid, verbose=False):
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def propagate_INT_lr_bits(database, tiles_by_grid, verbose=False):
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'''Populate segment base addresses: L/R along INT column'''
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'''
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Create BRAM base addresses based on nearby CLBs
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ie if we have a BRAM_L, compute as nearby CLB_R base address + offset
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'''
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int_frames, int_words, _ = localutil.get_entry('INT', 'CLB_IO_CLK')
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verbose and print('')
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for tile in database:
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@ -174,17 +74,17 @@ def seg_base_addr_lr_INT(database, tiles_by_grid, verbose=False):
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grid_x = database[tile]["grid_x"]
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grid_y = database[tile]["grid_y"]
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framebase = int(database[tile]["bits"]["CLB_IO_CLK"]["baseaddr"], 0)
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wordbase = database[tile]["bits"]["CLB_IO_CLK"]["offset"]
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baseaddr = int(database[tile]["bits"]["CLB_IO_CLK"]["baseaddr"], 0)
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offset = database[tile]["bits"]["CLB_IO_CLK"]["offset"]
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if database[tile]["type"] == "INT_L":
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grid_x += 1
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framebase = framebase + 0x80
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baseaddr = baseaddr + 0x80
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elif database[tile]["type"] == "INT_R":
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grid_x -= 1
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framebase = framebase - 0x80
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baseaddr = baseaddr - 0x80
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else:
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assert 0
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assert 0, database[tile]["type"]
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# ROI at edge?
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if (grid_x, grid_y) not in tiles_by_grid:
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@ -200,203 +100,125 @@ def seg_base_addr_lr_INT(database, tiles_by_grid, verbose=False):
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else:
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assert 0
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add_int_bits(database, other_tile, framebase, wordbase)
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localutil.add_tile_bits(
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other_tile, database[other_tile], baseaddr, offset,
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int_frames, int_words)
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def seg_base_addr_up_INT(database, segments, tiles_by_grid, verbose=False):
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'''Populate segment base addresses: Up along INT/HCLK columns'''
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def propagate_INT_bits_in_column(database, tiles_by_grid):
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""" Propigate INT offsets up and down INT columns.
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verbose and print('')
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# Copy the initial list containing only base addresses
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# and soon to have derived addresses
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src_segment_names = list()
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for segment_name in segments.keys():
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if "baseaddr" in segments[segment_name]:
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src_segment_names.append(segment_name)
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verbose and print('up_INT: %u base addresses' % len(src_segment_names))
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for src_segment_name in sorted(src_segment_names):
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src_segment = segments[src_segment_name]
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for block_type, (framebase,
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wordbase) in sorted(src_segment["baseaddr"].items()):
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verbose and print(
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'up_INT: %s: %s.0x%08X:%u' %
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(src_segment_name, block_type, framebase, wordbase))
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def process_CLB_IO_CLK(wordbase):
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'''
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Lookup interconnect tile associated with this segment
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Use it to locate in the grid, and find other segments related by tile offset
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'''
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for inttile in list(get_inttile(database, src_segment)) + list(
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get_iobtile(database, src_segment)):
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verbose and print(
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' up_INT CLB_IO_CLK: %s => inttile %s' %
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(src_segment_name, inttile),
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file=sys.stderr)
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grid_x = database[inttile]["grid_x"]
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grid_y = database[inttile]["grid_y"]
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for dst_tile, wordbase in localutil.propagate_up_INT(
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grid_x, grid_y, database, tiles_by_grid, wordbase):
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if 'segment' not in dst_tile:
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print(
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'WARNING: Missing segment for {} ({}, {}) {}'.
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format(
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tiles_by_grid[(grid_x, grid_y)], grid_x,
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grid_y, dst_tile))
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continue
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#verbose and print(' dst_tile', dst_tile)
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if 'segment' in dst_tile:
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dst_segment_name = dst_tile["segment"]
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#verbose and print('up_INT: %s => %s' % (src_segment_name, dst_segment_name))
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segments[dst_segment_name].setdefault(
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"baseaddr",
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{})[block_type] = [framebase, wordbase]
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def process_BLOCK_RAM(wordbase):
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'''
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Lookup BRAM0 tile associated with this segment
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Use it to locate in the grid, and find other BRAM0 related by tile offset
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From minitest:
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build/roi_bramd_bit01.diff (lowest BRAM coordinate)
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> bit_00c00000_000_00
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build/roi_bramds_bit01.diff
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> bit_00c00000_000_00
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> bit_00c00000_010_00
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> bit_00c00000_020_00
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> bit_00c00000_030_00
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> bit_00c00000_040_00
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> bit_00c00000_051_00
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> bit_00c00000_061_00
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> bit_00c00000_071_00
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> bit_00c00000_081_00
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> bit_00c00000_091_00
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'''
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src_tile_name = get_bramtile(database, src_segment)
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verbose and print(
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' up_INT BLOCK_RAM: %s => %s' %
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(src_segment_name, src_tile_name))
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grid_x = database[src_tile_name]["grid_x"]
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grid_y = database[src_tile_name]["grid_y"]
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for i in range(9):
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grid_y -= 5
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wordbase += 10
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# Skip HCLK
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if i == 4:
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grid_y -= 1
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wordbase += 1
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# FIXME: PCIE block cuts out some BRAM
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# this messes up algorithm as is and may cause this to fail
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if grid_y < 0:
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continue
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dst_tile_name = tiles_by_grid[(grid_x, grid_y)]
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dst_tile = database[dst_tile_name]
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assert nolr(dst_tile['type']) == 'BRAM', dst_tile
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dst_segment_name = dst_tile["segment"]
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verbose and print(
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' up_INT BLOCK_RAM: %s => %s' %
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(dst_segment_name, dst_tile_name))
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assert 'BRAM0' in dst_segment_name
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segments[dst_segment_name].setdefault(
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"baseaddr", {})[block_type] = [framebase, wordbase]
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{
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'CLB_IO_CLK': process_CLB_IO_CLK,
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'BLOCK_RAM': process_BLOCK_RAM,
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}[block_type](
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wordbase)
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def db_add_bits(database, segments):
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'''Transfer segment data into tiles'''
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for segment_name in segments.keys():
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if 'baseaddr' not in segments[segment_name]:
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continue
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for block_type, (baseaddr,
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offset) in segments[segment_name]["baseaddr"].items():
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for tile_name in segments[segment_name]["tiles"]:
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tile_type = database[tile_name]["type"]
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entry = localutil.get_entry(nolr(tile_type), block_type)
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if entry is None:
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# Other types are rare, not expected to have these
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if block_type == "CLB_IO_CLK":
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raise ValueError("Unknown tile type %s" % tile_type)
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continue
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frames, words, height = entry
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if frames:
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# if we have a width, we should have a height
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assert frames and words
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||||
localutil.add_tile_bits(
|
||||
tile_name, database[tile_name], baseaddr, offset,
|
||||
frames, words, height)
|
||||
|
||||
|
||||
def add_hclk_bits(database, tiles_by_grid):
|
||||
""" Propigate HCLK baseaddr and wordbase from INT tiles above and below.
|
||||
|
||||
HCLK tiles are located between two INT tiles. The offset seperate between
|
||||
these two tiles should be 3. The HCLK tile has an offset of 2 from the
|
||||
lower INT offset and an offset of 1 from the upper INT offset.
|
||||
INT columns appear to be fairly regular, where starting from offset 0,
|
||||
INT tiles next to INT tiles increase the word offset by 2. The HCLK tile
|
||||
is surrounded above and sometimes below by an INT tile. Because the HCLK
|
||||
tile only useds one word, the offset increase by one at the HCLK.
|
||||
|
||||
"""
|
||||
|
||||
_, int_words, _ = localutil.get_entry('INT', 'CLB_IO_CLK')
|
||||
seen_int = set()
|
||||
|
||||
int_frames, int_words, _ = localutil.get_entry('INT', 'CLB_IO_CLK')
|
||||
hclk_frames, hclk_words, _ = localutil.get_entry('HCLK', 'CLB_IO_CLK')
|
||||
|
||||
for tile_name in sorted(database.keys()):
|
||||
tile = database[tile_name]
|
||||
|
||||
if tile['type'] not in ['HCLK_L', 'HCLK_R']:
|
||||
if tile['type'] not in ['INT_L', 'INT_R']:
|
||||
continue
|
||||
|
||||
tile_below = tiles_by_grid[(tile['grid_x'], tile['grid_y'] + 1)]
|
||||
tile_above = tiles_by_grid[(tile['grid_x'], tile['grid_y'] - 1)]
|
||||
l_or_r = tile['type'][-1]
|
||||
|
||||
expected_tile_type = 'INT_{}'.format(tile['type'][-1])
|
||||
|
||||
assert database[tile_below]['type'] == expected_tile_type, (
|
||||
tile_name, tile_below)
|
||||
assert database[tile_above]['type'] == expected_tile_type, (
|
||||
tile_name, tile_above)
|
||||
|
||||
if not database[tile_below]['bits']:
|
||||
continue
|
||||
if not database[tile_above]['bits']:
|
||||
if not tile['bits']:
|
||||
continue
|
||||
|
||||
bits_below = database[tile_below]['bits']['CLB_IO_CLK']
|
||||
bits_above = database[tile_above]['bits']['CLB_IO_CLK']
|
||||
if tile_name in seen_int:
|
||||
continue
|
||||
|
||||
assert bits_below['baseaddr'] == bits_above['baseaddr'], (
|
||||
tile_name, bits_below['baseaddr'], bits_above['baseaddr'])
|
||||
# Walk down INT column
|
||||
while True:
|
||||
seen_int.add(tile_name)
|
||||
|
||||
offset_below = bits_below['offset']
|
||||
offset_above = bits_above['offset']
|
||||
next_tile = tiles_by_grid[(tile['grid_x'], tile['grid_y'] + 1)]
|
||||
next_tile_type = database[next_tile]['type']
|
||||
|
||||
assert offset_above - offset_below == (int_words + hclk_words), (
|
||||
tile_name, offset_below, offset_above, int_words + hclk_words)
|
||||
if tile['bits']['CLB_IO_CLK']['offset'] == 0:
|
||||
assert next_tile_type in ['B_TERM_INT', 'BRKH_INT', 'BRKH_B_TERM_INT'], next_tile_type
|
||||
break
|
||||
|
||||
localutil.add_tile_bits(
|
||||
tile_name,
|
||||
database[tile_name],
|
||||
baseaddr=int(bits_below['baseaddr'], 0),
|
||||
offset=offset_below + int_words,
|
||||
frames=hclk_frames,
|
||||
words=hclk_words)
|
||||
baseaddr = int(tile['bits']['CLB_IO_CLK']['baseaddr'], 0)
|
||||
offset = tile['bits']['CLB_IO_CLK']['offset']
|
||||
|
||||
if tile['type'].startswith('INT_') and next_tile_type == tile['type']:
|
||||
# INT next to INT
|
||||
offset -= int_words
|
||||
localutil.add_tile_bits(
|
||||
next_tile, database[next_tile], baseaddr, offset,
|
||||
int_frames, int_words)
|
||||
elif tile['type'].startswith('INT_'):
|
||||
# INT above HCLK
|
||||
assert next_tile_type.startswith('HCLK_{}'.format(l_or_r)), next_tile_type
|
||||
|
||||
offset -= hclk_words
|
||||
localutil.add_tile_bits(
|
||||
next_tile, database[next_tile], baseaddr, offset,
|
||||
hclk_frames, hclk_words)
|
||||
else:
|
||||
# HCLK above INT
|
||||
assert tile['type'].startswith('HCLK_{}'.format(l_or_r)), tile['type']
|
||||
if next_tile_type == 'INT_{}'.format(l_or_r):
|
||||
offset -= int_words
|
||||
localutil.add_tile_bits(
|
||||
next_tile, database[next_tile], baseaddr, offset,
|
||||
int_frames, int_words)
|
||||
else:
|
||||
# Handle special case column where the PCIE tile is present.
|
||||
assert next_tile_type in ['PCIE_NULL'], next_tile_type
|
||||
break
|
||||
|
||||
|
||||
tile_name = next_tile
|
||||
tile = database[tile_name]
|
||||
|
||||
# Walk up INT column
|
||||
while True:
|
||||
seen_int.add(tile_name)
|
||||
|
||||
next_tile = tiles_by_grid[(tile['grid_x'], tile['grid_y'] - 1)]
|
||||
next_tile_type = database[next_tile]['type']
|
||||
|
||||
if tile['bits']['CLB_IO_CLK']['offset'] == 99:
|
||||
assert next_tile_type in ['T_TERM_INT', 'BRKH_INT', 'BRKH_TERM_INT'], next_tile_type
|
||||
break
|
||||
|
||||
baseaddr = int(tile['bits']['CLB_IO_CLK']['baseaddr'], 0)
|
||||
offset = tile['bits']['CLB_IO_CLK']['offset']
|
||||
|
||||
if tile['type'].startswith('INT_') and next_tile_type == tile['type']:
|
||||
# INT next to INT
|
||||
offset += int_words
|
||||
localutil.add_tile_bits(
|
||||
next_tile, database[next_tile], baseaddr, offset,
|
||||
int_frames, int_words)
|
||||
elif tile['type'].startswith('INT_'):
|
||||
# INT below HCLK
|
||||
assert next_tile_type.startswith('HCLK_{}'.format(l_or_r)), next_tile_type
|
||||
|
||||
offset += int_words
|
||||
localutil.add_tile_bits(
|
||||
next_tile, database[next_tile], baseaddr, offset,
|
||||
hclk_frames, hclk_words)
|
||||
else:
|
||||
# HCLK below INT
|
||||
assert tile['type'].startswith('HCLK_{}'.format(l_or_r)), tile['type']
|
||||
assert next_tile_type == 'INT_{}'.format(l_or_r), next_tile_type
|
||||
|
||||
offset += hclk_words
|
||||
localutil.add_tile_bits(
|
||||
next_tile, database[next_tile], baseaddr, offset,
|
||||
int_frames, int_words)
|
||||
|
||||
tile_name = next_tile
|
||||
tile = database[tile_name]
|
||||
|
||||
|
||||
def run(json_in_fn, json_out_fn, int_tdb=None, verbose=False):
|
||||
|
|
@ -404,7 +226,8 @@ def run(json_in_fn, json_out_fn, int_tdb=None, verbose=False):
|
|||
database = json.load(open(json_in_fn, "r"))
|
||||
tiles_by_grid = make_tiles_by_grid(database)
|
||||
|
||||
add_hclk_bits(database, tiles_by_grid)
|
||||
propagate_INT_lr_bits(database, tiles_by_grid, verbose=verbose)
|
||||
propagate_INT_bits_in_column(database, tiles_by_grid)
|
||||
|
||||
# Save
|
||||
xjson.pprint(open(json_out_fn, "w"), database)
|
||||
|
|
|
|||
|
|
@ -49,7 +49,6 @@ proc loc_pins {} {
|
|||
set tile [get_tiles -of_objects $site]
|
||||
|
||||
set pin [dict get $io_pin_sites $site]
|
||||
|
||||
set_property -dict "PACKAGE_PIN $pin IOSTANDARD LVCMOS33" $port
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -8,6 +8,7 @@ import random
|
|||
random.seed(int(os.getenv("SEED"), 16))
|
||||
from prjxray import util
|
||||
from prjxray.db import Database
|
||||
import re
|
||||
|
||||
|
||||
def gen_sites():
|
||||
|
|
@ -31,7 +32,9 @@ def gen_sites():
|
|||
if len(sites) == 0:
|
||||
continue
|
||||
|
||||
sites.sort()
|
||||
sites_y = [int(re.match('IDELAY_X[0-9]+Y([0-9]+)', site).group(1)) for site in sites]
|
||||
|
||||
sites, _ = zip(*sorted(zip(sites, sites_y), key=lambda x: x[1]))
|
||||
|
||||
if gridinfo.tile_type[0] == 'L':
|
||||
int_grid_x = loc.grid_x + 3
|
||||
|
|
@ -47,7 +50,10 @@ def gen_sites():
|
|||
]
|
||||
|
||||
pad_gridinfo = grid.gridinfo_at_loc((pad_grid_x, loc.grid_y))
|
||||
pad_sites = sorted(pad_gridinfo.sites.keys())
|
||||
|
||||
pad_sites = pad_gridinfo.sites.keys()
|
||||
pad_sites_y = [int(re.match('IOB_X[0-9]+Y([0-9]+)', site).group(1)) for site in pad_sites]
|
||||
pad_sites, _ = zip(*sorted(zip(pad_sites, pad_sites_y), key=lambda x: x[1]))
|
||||
|
||||
if not gridinfo.tile_type.endswith("_SING"):
|
||||
int_tile_locs.append((int_grid_x, loc.grid_y - 1))
|
||||
|
|
|
|||
|
|
@ -39,6 +39,9 @@ def main():
|
|||
if 'INT_INTERFACE' in tile_type:
|
||||
continue
|
||||
|
||||
if 'BRKH' in tile_type:
|
||||
continue
|
||||
|
||||
have_bits = 0
|
||||
for tile_name, gridinfo in tiles:
|
||||
total_tile_count += 1
|
||||
|
|
|
|||
Loading…
Reference in New Issue