mirror of https://github.com/openXC7/prjxray.git
Working complete HROW pip fuzzer.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman
parent
023cd55bb1
commit
c2df5c97eb
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@ -84,7 +84,7 @@ def run(fn_in, fn_out, verbose=False):
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("bram_block/build/segbits_tilegrid.tdb", 128, 10),
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("clb/build/segbits_tilegrid.tdb", 36, 2),
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("dsp/build/segbits_tilegrid.tdb", 28, 10),
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("clk_hrow/build/segbits_tilegrid.tdb", 30, 7),
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("clk_hrow/build/segbits_tilegrid.tdb", 30, 18),
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("clk_bufg/build/segbits_tilegrid.tdb", 30, 8),
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("clb_int/build/segbits_tilegrid.tdb", int_frames, int_words),
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("iob_int/build/segbits_tilegrid.tdb", int_frames, int_words),
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@ -1,4 +1,4 @@
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N ?= 5
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GENERATE_ARGS?="--oneval 1 --design params.csv --dword 1 --dframe 1A"
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GENERATE_ARGS?="--oneval 1 --design params.csv --dword 6 --dframe 1A"
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include ../fuzzaddr/common.mk
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@ -233,7 +233,7 @@ def propagate_rebuf(database, tiles_by_grid):
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rebuf_below]['type']
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assert database[tile_name]['bits']['CLB_IO_CLK'][
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'offset'] == 47, database[tile_name]['bits']['CLB_IO_CLK']
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'offset'] == 42, database[tile_name]['bits']['CLB_IO_CLK']
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database[rebuf_below]['bits'] = copy.deepcopy(
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database[tile_name]['bits'])
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database[rebuf_below]['bits']['CLB_IO_CLK']['offset'] = 73
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@ -5,12 +5,15 @@ PIPLIST_TCL=$(FUZDIR)/clk_hrow_pip_list.tcl
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ifeq (${XRAY_PART}, xc7z010clg400-1)
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# xc7z010clg400-1 is missing some side clock connections, so these bits cannot
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# be documented.
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# FIXME: Use EXCLUDE_RE rather than complicated include RE.
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TODO_RE="[^\.]+\.CLK_HROW_CK_MUX_OUT_[LR][0-9]+\.CLK_HROW_.*[KR_][0-9]+"
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TODO_EXCLUDE_RE="^CLK_HROW_BOT_R.*CASCIN[0-9]+$$"
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else
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TODO_RE=".*"
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TODO_EXCLUDE_RE="^CLK_HROW_BOT_R.*CASCIN[0-9]+$$"
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endif
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MAKETODO_FLAGS=--sides "bot_r,top_r" --pip-type ${PIP_TYPE} --seg-type clk_hrow --re $(TODO_RE)
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MAKETODO_FLAGS=--sides "bot_r,top_r" --pip-type ${PIP_TYPE} --seg-type clk_hrow --re $(TODO_RE) --exclude-re $(TODO_EXCLUDE_RE)
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N = 50
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# These PIPs all appear to be either a 2 bit solutions.
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@ -20,39 +23,49 @@ A_PIPLIST=clk_hrow_bot_r.txt
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include ../pip_loop.mk
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database: build/segbits_clk_hrow.db
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build/cmt_regions.csv: output_cmt.tcl
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mkdir -p build
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cd build/ && ${XRAY_VIVADO} -mode batch -source ${FUZDIR}/output_cmt.tcl
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build/segbits_clk_hrow.rdb: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} ${SEGMATCH_FLAGS} -o build/segbits_clk_hrow.rdb \
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$(shell find build -name segdata_clk_hrow_top_r.txt) \
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$(shell find build -name segdata_clk_hrow_bot_r.txt)
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build/segbits_clk_hrow.db: build/segbits_clk_hrow.rdb
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database: build/segbits_clk_hrow_bot_r.rdb build/segbits_clk_hrow_top_r.rdb
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${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf \
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--seg-fn-in build/segbits_clk_hrow.rdb \
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--seg-fn-out build/segbits_clk_hrow.db
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--seg-fn-in build/segbits_clk_hrow_top_r.rdb \
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--seg-fn-out build/segbits_clk_hrow_top_r.db
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${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf \
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--seg-fn-in build/segbits_clk_hrow_bot_r.rdb \
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--seg-fn-out build/segbits_clk_hrow_bot_r.db
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# Keep a copy to track iter progress
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cp build/segbits_clk_hrow.rdb build/$(ITER)/segbits_clk_hrow.rdb
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cp build/segbits_clk_hrow_top_r.rdb build/$(ITER)/segbits_clk_hrow_top_r.rdb
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cp build/segbits_clk_hrow_bot_r.rdb build/$(ITER)/segbits_clk_hrow_bot_r.rdb
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${XRAY_MASKMERGE} build/mask_clk_hrow.db \
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$(shell find build -name segdata_clk_hrow_top_r.txt) \
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${XRAY_MASKMERGE} build/mask_clk_hrow_top_r.db \
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$(shell find build -name segdata_clk_hrow_top_r.txt)
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${XRAY_MASKMERGE} build/mask_clk_hrow_bot_r.db \
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$(shell find build -name segdata_clk_hrow_bot_r.txt)
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# Clobber existing .db to eliminate potential conflicts
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rm -f build/database/${XRAY_DATABASE}/*
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cp ${XRAY_DATABASE_DIR}/${XRAY_DATABASE}/segbits*.db build/database/${XRAY_DATABASE}
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XRAY_DATABASE_DIR=${FUZDIR}/build/database ${XRAY_MERGEDB} clk_hrow_bot_r build/segbits_clk_hrow.db
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XRAY_DATABASE_DIR=${FUZDIR}/build/database ${XRAY_MERGEDB} clk_hrow_top_r build/segbits_clk_hrow.db
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XRAY_DATABASE_DIR=${FUZDIR}/build/database ${XRAY_MERGEDB} clk_hrow_bot_r build/segbits_clk_hrow_bot_r.db
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XRAY_DATABASE_DIR=${FUZDIR}/build/database ${XRAY_MERGEDB} clk_hrow_top_r build/segbits_clk_hrow_top_r.db
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build/cmt_regions.csv: output_cmt.tcl
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mkdir -p build
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cd build/ && ${XRAY_VIVADO} -mode batch -source ${FUZDIR}/output_cmt.tcl
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generate: $(SPECIMENS_OK)
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build/segbits_clk_hrow_top_r.rdb: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} ${SEGMATCH_FLAGS} -o build/segbits_clk_hrow_top_r.rdb \
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$(shell find build -name segdata_clk_hrow_top_r.txt)
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build/segbits_clk_hrow_bot_r.rdb: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} ${SEGMATCH_FLAGS} -o build/segbits_clk_hrow_bot_r.rdb \
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$(shell find build -name segdata_clk_hrow_bot_r.txt)
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build/segbits_clk_hrow.db: build/segbits_clk_hrow_top_.rdb
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pushdb: database
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${XRAY_MERGEDB} clk_hrow_bot_r build/segbits_clk_hrow.db
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${XRAY_MERGEDB} clk_hrow_top_r build/segbits_clk_hrow.db
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${XRAY_MERGEDB} mask_clk_hrow_bot_r build/mask_clk_hrow.db
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${XRAY_MERGEDB} mask_clk_hrow_top_r build/mask_clk_hrow.db
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${XRAY_MERGEDB} clk_hrow_bot_r build/segbits_clk_hrow_bot_r.db
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${XRAY_MERGEDB} clk_hrow_top_r build/segbits_clk_hrow_top_r.db
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${XRAY_MERGEDB} mask_clk_hrow_bot_r build/mask_clk_hrow_bot_r.db
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${XRAY_MERGEDB} mask_clk_hrow_top_r build/mask_clk_hrow_top_r.db
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.PHONY: database pushdb
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.PHONY: database pushdb generate
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@ -3,7 +3,6 @@
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import os
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import os.path
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from prjxray.segmaker import Segmaker
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import pprint
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def main():
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@ -12,6 +11,7 @@ def main():
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tiledata = {}
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pipdata = {}
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clk_list = {}
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casco_list = {}
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ignpip = set()
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with open(os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
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@ -21,9 +21,13 @@ def main():
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if tile_type not in pipdata:
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pipdata[tile_type] = []
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clk_list[tile_type] = set()
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casco_list[tile_type] = set()
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pipdata[tile_type].append((src, dst))
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if 'CASCO' in dst:
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casco_list[tile_type].add(dst)
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if dst.startswith('CLK_HROW_CK_MUX_OUT_'):
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clk_list[tile_type].add(src)
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@ -34,9 +38,13 @@ def main():
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if tile_type not in pipdata:
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pipdata[tile_type] = []
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clk_list[tile_type] = set()
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casco_list[tile_type] = set()
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pipdata[tile_type].append((src, dst))
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if 'CASCO' in dst:
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casco_list[tile_type].add(dst)
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if dst.startswith('CLK_HROW_CK_MUX_OUT_'):
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clk_list[tile_type].add(src)
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@ -78,7 +86,6 @@ def main():
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active_gclks = {}
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active_clks = {}
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for tile, pips_srcs_dsts in tiledata.items():
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tile_type = pips_srcs_dsts["type"]
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pips = pips_srcs_dsts["pips"]
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@ -87,15 +94,13 @@ def main():
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active_clks[tile] = set()
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for src, dst in pips_srcs_dsts["pips"]:
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if dst.startswith('CLK_HROW_CK_MUX_OUT_'):
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active_clks[tile].add(src)
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active_clks[tile].add(src)
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if 'GCLK' in src:
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if src not in active_gclks:
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active_gclks[src] = set()
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if 'GCLK' in src:
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if src not in active_gclks:
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active_gclks[src] = set()
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active_gclks[src].add(tile)
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active_gclks[src].add(tile)
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for src, dst in pipdata[tile_type]:
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if (src, dst) in ignpip:
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@ -121,7 +121,7 @@ proc route_todo {} {
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}
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set origin_node [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]]
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set destination_nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]]
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set destination_nodes [filter [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] {NAME =~ *CLK_HROW*}]
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route_design -unroute -nets $net
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set new_route [find_routing_path -to $target_node -from $origin_node]
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puts "Origin node: $origin_node"
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@ -151,6 +151,7 @@ proc run {} {
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-161}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-123}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-13}]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets]
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@ -3,7 +3,7 @@ set_property design_mode PinPlanning [current_fileset]
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open_io_design -name io_1
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set fp [open "cmt_regions.csv" "w"]
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foreach site_type {MMCME2_ADV PLLE2_ADV BUFHCE} {
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foreach site_type {MMCME2_ADV PLLE2_ADV BUFHCE BUFR} {
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foreach site [get_sites -filter "SITE_TYPE == $site_type"] {
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puts $fp "$site,[get_property CLOCK_REGION $site]"
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}
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@ -1,11 +1,17 @@
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""" Emits top.v's for various BUFHCE routing inputs. """
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import os
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import random
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import re
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random.seed(int(os.getenv("SEED"), 16))
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from prjxray import util
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from prjxray import verilog
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from prjxray.db import Database
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from prjxray.lut_maker import LutMaker
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from io import StringIO
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CMT_XY_FUN = util.create_xy_fun(prefix='')
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BUFGCTRL_XY_FUN = util.create_xy_fun('BUFGCTRL_')
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BUFHCE_XY_FUN = util.create_xy_fun('BUFHCE_')
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def gen_sites(desired_site_type):
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@ -17,7 +23,7 @@ def gen_sites(desired_site_type):
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gridinfo = grid.gridinfo_at_loc(loc)
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for site, site_type in gridinfo.sites.items():
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if site_type == desired_site_type:
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yield site
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yield loc, gridinfo.tile_type, site
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def gen_bufhce_sites():
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@ -59,8 +65,10 @@ class ClockSources(object):
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self.merged_sources = {}
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self.source_to_cmt = {}
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self.used_sources_from_cmt = {}
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self.sources_by_loc = {}
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self.active_cmt_ports = {}
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def add_clock_source(self, source, cmt):
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def add_clock_source(self, source, cmt, loc=None):
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""" Adds a source from a specific CMT.
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cmt='ANY' indicates that this source can be routed to any CMT.
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@ -73,6 +81,14 @@ class ClockSources(object):
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source] == cmt, source
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self.source_to_cmt[source] = cmt
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self.add_bufg_clock_source(source, cmt, loc)
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def add_bufg_clock_source(self, source, cmt, loc):
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if loc not in self.sources_by_loc:
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self.sources_by_loc[loc] = []
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self.sources_by_loc[loc].append((cmt, source))
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def get_random_source(self, cmt):
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""" Get a random source that is routable to the specific CMT.
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@ -113,12 +129,91 @@ class ClockSources(object):
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if source_cmt != 'ANY' and len(
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self.used_sources_from_cmt[source_cmt]) > 14:
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print('//', self.used_sources_from_cmt)
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self.used_sources_from_cmt[source_cmt].remove(source)
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return None
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else:
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return source
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def get_bufg_source(self, loc, tile_type, site, todos, i_wire, used_only):
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bufg_sources = []
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top = '_TOP_' in tile_type
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bottom = '_BOT_' in tile_type
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assert top ^ bottom, tile_type
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if top:
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for src_loc, cmt_sources in self.sources_by_loc.items():
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if src_loc is None:
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continue
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if src_loc.grid_y <= loc.grid_y:
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bufg_sources.extend(cmt_sources)
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elif bottom:
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for src_loc, cmt_sources in self.sources_by_loc.items():
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if src_loc is None:
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continue
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if src_loc.grid_y > loc.grid_y:
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bufg_sources.extend(cmt_sources)
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# CLK_HROW_TOP_R_CK_BUFG_CASCO0 -> CLK_BUFG_BUFGCTRL0_I0
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# CLK_HROW_TOP_R_CK_BUFG_CASCO22 -> CLK_BUFG_BUFGCTRL11_I0
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# CLK_HROW_TOP_R_CK_BUFG_CASCO23 -> CLK_BUFG_BUFGCTRL11_I1
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# CLK_HROW_BOT_R_CK_BUFG_CASCO27 -> CLK_BUFG_BUFGCTRL13_I1
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x, y = BUFGCTRL_XY_FUN(site)
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assert x == 0
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y = y % 16
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assert i_wire in [0, 1], i_wire
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casco_wire = '{tile_type}_CK_BUFG_CASCO{casco_idx}'.format(
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tile_type=tile_type.replace('BUFG', 'HROW'),
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casco_idx=(y*2+i_wire))
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if casco_wire not in todos:
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return None
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target_wires = []
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need_bufr = False
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for src_wire in todos[casco_wire]:
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if 'BUFRCLK' in src_wire:
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need_bufr = True
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break
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for cmt, wire in bufg_sources:
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if 'BUFR' in wire:
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if need_bufr:
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target_wires.append((cmt, wire))
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else:
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target_wires.append((cmt, wire))
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random.shuffle(target_wires)
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for cmt, source in target_wires:
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if cmt == 'ANY':
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return source
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else:
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# Make sure to not try to import move than 14 sources from
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# the CMT, there is limited routing.
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if cmt not in self.used_sources_from_cmt:
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self.used_sources_from_cmt[cmt] = set()
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if source in self.used_sources_from_cmt[cmt]:
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return source
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elif used_only:
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continue
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if len(self.used_sources_from_cmt[cmt]) < 14:
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self.used_sources_from_cmt[cmt].add(source)
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return source
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else:
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continue
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return None
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def check_allowed(mmcm_pll_dir, cmt):
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""" Check whether the CMT specified is in the allowed direction.
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@ -140,6 +235,45 @@ def check_allowed(mmcm_pll_dir, cmt):
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else:
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assert False, mmcm_pll_dir
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def read_todo():
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dsts = {}
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with open(os.path.join('..', 'todo_all.txt')) as f:
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for l in f:
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tile_type, dst, src = l.strip().split('.')
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if dst not in dsts:
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dsts[dst] = set()
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dsts[dst].add(src)
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return dsts
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def need_int_connections(todos):
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for srcs in todos.values():
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for src in srcs:
|
||||
if re.search('INT_._.', src):
|
||||
return True
|
||||
|
||||
return False
|
||||
|
||||
def bufhce_in_todo(todos, site):
|
||||
if 'BUFHCE' in site:
|
||||
# CLK_HROW_CK_MUX_OUT_R9 -> X1Y9
|
||||
# CLK_HROW_CK_MUX_OUT_L11 -> X0Y35
|
||||
x, y = BUFHCE_XY_FUN(site)
|
||||
y = y % 12
|
||||
|
||||
if x == 0:
|
||||
lr = 'L'
|
||||
elif x == 1:
|
||||
lr = 'R'
|
||||
else:
|
||||
assert False, x
|
||||
|
||||
return 'CLK_HROW_CK_MUX_OUT_{lr}{y}'.format(lr=lr, y=y) in todos
|
||||
else:
|
||||
return True
|
||||
|
||||
def main():
|
||||
"""
|
||||
|
|
@ -166,26 +300,27 @@ module top();
|
|||
mmcm_pll_only = random.randint(0, 1)
|
||||
mmcm_pll_dir = random.choice(('ODD', 'EVEN', 'BOTH', 'NONE'))
|
||||
|
||||
todos = read_todo()
|
||||
|
||||
if not mmcm_pll_only:
|
||||
for _ in range(2):
|
||||
clock_sources.add_clock_source('one', 'ANY')
|
||||
clock_sources.add_clock_source('zero', 'ANY')
|
||||
if need_int_connections(todos):
|
||||
for _ in range(10):
|
||||
clock_sources.add_clock_source('one', 'ANY')
|
||||
clock_sources.add_clock_source('zero', 'ANY')
|
||||
|
||||
print("""
|
||||
wire zero = 0;
|
||||
wire one = 1;""")
|
||||
|
||||
for site in gen_sites('MMCME2_ADV'):
|
||||
for loc, _, site in gen_sites('MMCME2_ADV'):
|
||||
mmcm_clocks = [
|
||||
'mmcm_clock_{site}_{idx}'.format(site=site, idx=idx)
|
||||
for idx in range(13)
|
||||
]
|
||||
|
||||
if not check_allowed(mmcm_pll_dir, site_to_cmt[site]):
|
||||
continue
|
||||
|
||||
for clk in mmcm_clocks:
|
||||
clock_sources.add_clock_source(clk, site_to_cmt[site])
|
||||
if check_allowed(mmcm_pll_dir, site_to_cmt[site]):
|
||||
for clk in mmcm_clocks:
|
||||
clock_sources.add_clock_source(clk, site_to_cmt[site], loc)
|
||||
|
||||
print(
|
||||
"""
|
||||
|
|
@ -223,17 +358,15 @@ module top();
|
|||
c12=mmcm_clocks[12],
|
||||
))
|
||||
|
||||
for site in gen_sites('PLLE2_ADV'):
|
||||
for loc, _, site in gen_sites('PLLE2_ADV'):
|
||||
pll_clocks = [
|
||||
'pll_clock_{site}_{idx}'.format(site=site, idx=idx)
|
||||
for idx in range(6)
|
||||
]
|
||||
|
||||
if not check_allowed(mmcm_pll_dir, site_to_cmt[site]):
|
||||
continue
|
||||
|
||||
for clk in pll_clocks:
|
||||
clock_sources.add_clock_source(clk, site_to_cmt[site])
|
||||
if check_allowed(mmcm_pll_dir, site_to_cmt[site]):
|
||||
for clk in pll_clocks:
|
||||
clock_sources.add_clock_source(clk, site_to_cmt[site], loc)
|
||||
|
||||
print(
|
||||
"""
|
||||
|
|
@ -257,30 +390,65 @@ module top();
|
|||
c5=pll_clocks[5],
|
||||
))
|
||||
|
||||
for loc, _, site in gen_sites('BUFR'):
|
||||
clock_sources.add_bufg_clock_source('O_{site}'.format(site=site), site_to_cmt[site], loc)
|
||||
print("""
|
||||
wire O_{site};
|
||||
(* KEEP, DONT_TOUCH, LOC = "{site}" *)
|
||||
BUFR bufr_{site} (
|
||||
.O(O_{site})
|
||||
);""".format(site=site))
|
||||
|
||||
luts = LutMaker()
|
||||
bufhs = StringIO()
|
||||
bufgs = StringIO()
|
||||
|
||||
gclks = []
|
||||
for site in sorted(gen_sites("BUFGCTRL"),
|
||||
key=util.create_xy_fun('BUFGCTRL_')):
|
||||
wire_name = 'clk_{}'.format(site)
|
||||
for _, _, site in sorted(gen_sites("BUFGCTRL"),
|
||||
key=lambda x: BUFGCTRL_XY_FUN(x[2])):
|
||||
wire_name = 'gclk_{}'.format(site)
|
||||
gclks.append(wire_name)
|
||||
|
||||
if not mmcm_pll_only:
|
||||
clock_sources.add_clock_source(wire_name, 'ANY')
|
||||
|
||||
print("""
|
||||
wire {wire_name};
|
||||
""".format(wire_name=wire_name))
|
||||
print(
|
||||
"""
|
||||
wire {wire_name};
|
||||
wire I1_{site};
|
||||
wire I0_{site};
|
||||
(* KEEP, DONT_TOUCH, LOC = "{site}" *)
|
||||
BUFG bufg_{site} (
|
||||
.O({wire_name})
|
||||
BUFGCTRL bufg_{site} (
|
||||
.O({wire_name}),
|
||||
.S1({s1net}),
|
||||
.S0({s0net}),
|
||||
.IGNORE1({ignore1net}),
|
||||
.IGNORE0({ignore0net}),
|
||||
.I1(I1_{site}),
|
||||
.I0(I0_{site}),
|
||||
.CE1({ce1net}),
|
||||
.CE0({ce0net})
|
||||
);
|
||||
""".format(
|
||||
site=site,
|
||||
wire_name=wire_name,
|
||||
))
|
||||
s1net=luts.get_next_output_net(),
|
||||
s0net=luts.get_next_output_net(),
|
||||
ignore1net=luts.get_next_output_net(),
|
||||
ignore0net=luts.get_next_output_net(),
|
||||
ce1net=luts.get_next_output_net(),
|
||||
ce0net=luts.get_next_output_net(),
|
||||
), file=bufgs)
|
||||
|
||||
|
||||
any_bufhce = False
|
||||
for tile_name, sites in gen_bufhce_sites():
|
||||
for site in sites:
|
||||
if not bufhce_in_todo(todos, site):
|
||||
continue
|
||||
|
||||
any_bufhce = True
|
||||
print(
|
||||
"""
|
||||
|
|
@ -291,10 +459,11 @@ module top();
|
|||
);
|
||||
""".format(
|
||||
site=site,
|
||||
))
|
||||
), file=bufhs)
|
||||
|
||||
if random.random() > .05:
|
||||
wire_name = clock_sources.get_random_source(site_to_cmt[site])
|
||||
|
||||
if wire_name is None:
|
||||
continue
|
||||
|
||||
|
|
@ -302,7 +471,7 @@ module top();
|
|||
assign I_{site} = {wire_name};""".format(
|
||||
site=site,
|
||||
wire_name=wire_name,
|
||||
))
|
||||
), file=bufhs)
|
||||
|
||||
|
||||
if not any_bufhce:
|
||||
|
|
@ -311,16 +480,52 @@ module top();
|
|||
print(
|
||||
"""
|
||||
(* KEEP, DONT_TOUCH, LOC = "{site}" *)
|
||||
BUFHCE buf_{site} (
|
||||
BUFHCE #(
|
||||
.INIT_OUT({INIT_OUT}),
|
||||
.CE_TYPE({CE_TYPE}),
|
||||
.IS_CE_INVERTED({IS_CE_INVERTED})
|
||||
) buf_{site} (
|
||||
.I({wire_name})
|
||||
);
|
||||
""".format(
|
||||
INIT_OUT=random.randint(0, 1),
|
||||
CE_TYPE=verilog.quote(
|
||||
random.choice(('SYNC', 'ASYNC'))),
|
||||
IS_CE_INVERTED = random.randint(0, 1),
|
||||
site=site,
|
||||
wire_name=gclks[0],
|
||||
))
|
||||
break
|
||||
break
|
||||
|
||||
for l in luts.create_wires_and_luts():
|
||||
print(l)
|
||||
|
||||
print(bufhs.getvalue())
|
||||
print(bufgs.getvalue())
|
||||
|
||||
used_only = random.random() < .25
|
||||
|
||||
for loc, tile_type, site in sorted(gen_sites("BUFGCTRL"),
|
||||
key=lambda x: BUFGCTRL_XY_FUN(x[2])):
|
||||
if random.randint(0, 1):
|
||||
wire_name = clock_sources.get_bufg_source(loc, tile_type, site, todos, 1, used_only)
|
||||
if wire_name is not None:
|
||||
print("""
|
||||
assign I1_{site} = {wire_name};""".format(
|
||||
site=site,
|
||||
wire_name=wire_name,
|
||||
))
|
||||
|
||||
if random.randint(0, 1):
|
||||
wire_name = clock_sources.get_bufg_source(loc, tile_type, site, todos, 0, used_only)
|
||||
if wire_name is not None:
|
||||
print("""
|
||||
assign I0_{site} = {wire_name};""".format(
|
||||
site=site,
|
||||
wire_name=wire_name,
|
||||
))
|
||||
|
||||
print("endmodule")
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -33,7 +33,7 @@ def load_pipfile(pipfile, verbose=False):
|
|||
return todos, tile_type
|
||||
|
||||
|
||||
def maketodo(pipfile, dbfile, intre, not_endswith=None, verbose=False):
|
||||
def maketodo(pipfile, dbfile, intre, exclude_re=None, not_endswith=None, verbose=False):
|
||||
'''
|
||||
db files start with INT., but pipfile lines start with INT_L
|
||||
Normalize by removing before the first dot
|
||||
|
|
@ -75,8 +75,15 @@ def maketodo(pipfile, dbfile, intre, not_endswith=None, verbose=False):
|
|||
drops = 0
|
||||
lines = 0
|
||||
for line in todos:
|
||||
if re.match(intre, line) and (not_endswith is None
|
||||
or not line.endswith(not_endswith)):
|
||||
include = re.match(intre, line) is not None
|
||||
|
||||
if include and not_endswith is not None:
|
||||
include = not line.endswith(not_endswith)
|
||||
|
||||
if include and exclude_re is not None:
|
||||
include = re.match(exclude_re, line) is None
|
||||
|
||||
if include:
|
||||
print(line)
|
||||
else:
|
||||
drops += 1
|
||||
|
|
@ -94,6 +101,7 @@ def run(
|
|||
r,
|
||||
pip_type,
|
||||
seg_type,
|
||||
exclude_re=None,
|
||||
not_endswith=None,
|
||||
verbose=False):
|
||||
if db_dir is None:
|
||||
|
|
@ -117,7 +125,8 @@ def run(
|
|||
"%s/%s_%s.txt" % (pip_dir, pip_type, side),
|
||||
"%s/segbits_%s_%s.db" % (db_dir, seg_type, side),
|
||||
intre,
|
||||
not_endswith,
|
||||
exclude_re=exclude_re,
|
||||
not_endswith=not_endswith,
|
||||
verbose=verbose)
|
||||
|
||||
|
||||
|
|
@ -132,6 +141,7 @@ def main():
|
|||
parser.add_argument('--db-dir', default=None, help='')
|
||||
parser.add_argument('--pip-dir', default=None, help='')
|
||||
parser.add_argument('--re', required=True, help='')
|
||||
parser.add_argument('--exclude-re', required=False, default=None, help='')
|
||||
parser.add_argument('--pip-type', default="pips_int", help='')
|
||||
parser.add_argument('--seg-type', default="int", help='')
|
||||
parser.add_argument('--sides', default="l,r", help='')
|
||||
|
|
@ -146,6 +156,7 @@ def main():
|
|||
db_dir=args.db_dir,
|
||||
pip_dir=args.pip_dir,
|
||||
intre=args.re,
|
||||
exclude_re=args.exclude_re,
|
||||
sides=args.sides.split(','),
|
||||
l=args.l,
|
||||
r=args.r,
|
||||
|
|
|
|||
Loading…
Reference in New Issue