xadc: tilegrid support

Signed-off-by: John McMaster <johndmcmaster@gmail.com>
This commit is contained in:
John McMaster 2018-12-29 17:05:16 +01:00
parent 0594db79c6
commit 5acda63b46
5 changed files with 132 additions and 1 deletions

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@ -22,7 +22,7 @@ build/bram/deltas:
build/iob/deltas:
bash generate.sh build/iob iob
build/tilegrid_tdb.json: iob/build/segbits_tilegrid.tdb mmcm/build/segbits_tilegrid.tdb pll/build/segbits_tilegrid.tdb
build/tilegrid_tdb.json: add_tdb.py iob/build/segbits_tilegrid.tdb mmcm/build/segbits_tilegrid.tdb pll/build/segbits_tilegrid.tdb
python3 add_tdb.py --fn-in build/basicdb/tilegrid.json --fn-out build/tilegrid_tdb.json
iob/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
@ -34,6 +34,10 @@ mmcm/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
pll/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
cd pll && $(MAKE)
# FIXME: add monitor to ROI
monitor/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
cd monitor && $(MAKE)
build/tilegrid.json: generate_full.py build/tilegrid_tdb.json build/clb/deltas build/bram/deltas
cd build && python3 ${FUZDIR}/generate_full.py \
--json-in tilegrid_tdb.json --json-out ${BUILD_DIR}/tilegrid.json \

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@ -2,6 +2,7 @@
from prjxray import util
import json
import os
# Copied from generate_full.py
@ -101,6 +102,12 @@ def run(fn_in, fn_out, verbose=False):
# FIXME: height
("pll/build/segbits_tilegrid.tdb", 30, 101),
]
# FIXME: support XADC in ROI
if os.path.exists("monitor/build/segbits_tilegrid.tdb"):
# FIXME: height
tdb_fns.append(("monitor/build/segbits_tilegrid.tdb", 30, 101))
for (tdb_fn, frames, words) in tdb_fns:
for (tile, frame, wordidx) in load_db(tdb_fn):
tilej = database[tile]

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@ -0,0 +1,4 @@
N ?= 2
GENERATE_ARGS?="--oneval 1 --design params.csv --dframe 1C --dword 53 --dbit 24"
include ../fuzzaddr/common.mk

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@ -0,0 +1,26 @@
source "$::env(XRAY_DIR)/utils/utils.tcl"
proc run {} {
create_project -force -part $::env(XRAY_PART) design design
read_verilog top.v
synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
place_design
route_design
write_checkpoint -force design.dcp
write_bitstream -force design.bit
}
run

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@ -0,0 +1,90 @@
import os
import random
random.seed(int(os.getenv("SEED"), 16))
from prjxray import util
from prjxray import verilog
def gen_sites():
# yield ("MONITOR_BOT_X46Y79", "XADC_X0Y0")
for tile_name, site_name, _site_type in util.get_roi().gen_sites(['XADC']):
yield tile_name, site_name
def write_params(params):
pinstr = 'tile,val,site\n'
for tile, (site, val) in sorted(params.items()):
pinstr += '%s,%s,%s\n' % (tile, val, site)
open('params.csv', 'w').write(pinstr)
def run():
print(
'''
module top(input clk, stb, di, output do);
localparam integer DIN_N = 8;
localparam integer DOUT_N = 8;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
''')
params = {}
# only one for now, worry about later
sites = list(gen_sites())
assert len(sites) == 1, len(sites)
for (tile_name, site_name), isone in zip(sites,
util.gen_fuzz_states(len(sites))):
INIT_43 = isone
params[tile_name] = (site_name, INIT_43)
print(
'''
(* KEEP, DONT_TOUCH *)
XADC #(/*.LOC("%s"),*/ .INIT_43(%u)) dut_%s(
.BUSY(),
.DRDY(),
.EOC(),
.EOS(),
.JTAGBUSY(),
.JTAGLOCKED(),
.JTAGMODIFIED(),
.OT(),
.DO(),
.ALM(),
.CHANNEL(),
.MUXADDR(),
.CONVST(),
.CONVSTCLK(clk),
.DCLK(clk),
.DEN(),
.DWE(),
.RESET(),
.VN(),
.VP(),
.DI(),
.VAUXN(),
.VAUXP(),
.DADDR());
''' % (site_name, INIT_43, site_name))
print("endmodule")
write_params(params)
if __name__ == '__main__':
run()