Add missing FREQ_BB active feature.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

fuzzers/005-tilegrid/add_tdb.py

@@ -90,7 +90,7 @@ def run(fn_in, fn_out, verbose=False):
         ("iob", 42, 4),
         ("ioi", 42, 4),
         ("mmcm", 30, 101),
-        ("pll", 30, 26),
+        ("pll", 30, 27),
         ("monitor", 30, 101),
         ("bram", 28, 10),
         ("bram_block", 128, 10),

fuzzers/005-tilegrid/pll/Makefile

@@ -6,5 +6,5 @@
 #
 # SPDX-License-Identifier: ISC
 N ?= 6
-GENERATE_ARGS?="--oneval 1 --design params.csv --dframe 1C --dword 23"
+GENERATE_ARGS?="--oneval 1 --design params.csv --dframe 1C --dword 24"
 include ../fuzzaddr/common.mk

fuzzers/034-cmt-pll-pips/cmt_top_upper_t.tcl

@@ -28,9 +28,19 @@ proc print_tile_pips {tile_type filename} {
     close $fp
 }
 
+proc print_tile_wires {tile_type filename} {
+    set tile [lindex [get_tiles -filter "TYPE == $tile_type"] 0]
+    set fp [open $filename w]
+    foreach wire [lsort [get_wires -of_objects [get_tiles $tile]]] {
+        puts $fp "$tile_type [regsub {.*/} $wire ""]"
+    }
+}
+
 create_project -force -part $::env(XRAY_PART) design design
 set_property design_mode PinPlanning [current_fileset]
 open_io_design -name io_1
 
 print_tile_pips CMT_TOP_L_UPPER_T cmt_top_l_upper_t.txt
 print_tile_pips CMT_TOP_R_UPPER_T cmt_top_r_upper_t.txt
+print_tile_wires CMT_TOP_L_UPPER_T cmt_top_l_upper_t_wires.txt
+print_tile_wires CMT_TOP_R_UPPER_T cmt_top_r_upper_t_wires.txt

fuzzers/034-cmt-pll-pips/fixup_and_group.py

@@ -218,6 +218,21 @@ def main():
             tags_to_mask = [t for t in segbits.keys() if t.startswith(prefix)]
             mask_out_bits(segbits, segbits[tag], tags_to_mask)
 
+    tags_to_remove = set()
+    for tag, bits in segbits.items():
+        if len(bits) == 0:
+            tags_to_remove.add(tag)
+
+    for tag in tags_to_remove:
+        del segbits[tag]
+
+    for tag in segbits.keys():
+        if tag.endswith("_ACTIVE") and 'FREQ_BB' in tag:
+            m = re.search('FREQ_BB([0-9])', tag)
+            prefix = '.CMT_TOP_L_UPPER_T_FREQ_BB{}'.format(m.group(1))
+            tags_to_mask = [t for t in segbits.keys() if t.endswith(prefix)]
+            mask_out_bits(segbits, segbits[tag], tags_to_mask)
+
     # Find common bits
     bit_groups = find_common_bits_for_tag_groups(segbits, tag_groups)
     # Apply tag grouping

fuzzers/034-cmt-pll-pips/generate.py

@@ -12,7 +12,6 @@
 from prjxray.segmaker import Segmaker
 import os
 import os.path
-import itertools
 
 
 def bitfilter(frame, word):
@@ -30,8 +29,10 @@ def main():
     pipdata = {}
     ppipdata = {}
     ignpip = set()
+    all_clks = {}
 
     piplists = ['cmt_top_l_upper_t.txt', 'cmt_top_r_upper_t.txt']
+    wirelists = ['cmt_top_l_upper_t_wires.txt', 'cmt_top_r_upper_t_wires.txt']
     ppiplists = ['ppips_cmt_top_l_upper_t.db', 'ppips_cmt_top_r_upper_t.db']
 
     # Load PIP lists
@@ -43,8 +44,23 @@ def main():
                 tile_type, dst, src = l.strip().split('.')
                 if tile_type not in pipdata:
                     pipdata[tile_type] = []
+                    all_clks[tile_type] = set()
 
                 pipdata[tile_type].append((src, dst))
+                if dst.split('_')[-1].startswith('CLK'):
+                    all_clks[tile_type].add(src)
+
+    wiredata = {}
+    for wirelist in wirelists:
+        with open(os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
+                               'cmt_top', wirelist)) as f:
+            for l in f:
+                tile_type, wire = l.strip().split()
+
+                if tile_type not in wiredata:
+                    wiredata[tile_type] = set()
+
+                wiredata[tile_type].add(wire)
 
     # Load PPIP lists (to exclude them)
     print("Loading PPIP lists...")
@@ -111,6 +127,16 @@ def main():
                dst.startswith('CMT_TOP_L_UPPER_T_CLK'):
                 ignpip.add((src, dst))
 
+    active_wires = {}
+    with open("design_wires.txt", "r") as f:
+        for l in f:
+            tile, wire = l.strip().split('/')
+
+            if tile not in active_wires:
+                active_wires[tile] = set()
+
+            active_wires[tile].add(wire)
+
     tags = {}
 
     # Populate IN_USE tags
@@ -121,11 +147,11 @@ def main():
         tags[tile]["IN_USE"] = int(in_use)
 
     # Populate PIPs
+    active_clks = {}
     for tile in tags.keys():
         tile_type = tile.rsplit("_", maxsplit=1)[0]
 
         in_use = tags[tile]["IN_USE"]
-        internal_feedback = False
 
         if not in_use:
             active_pips = []
@@ -143,8 +169,30 @@ def main():
             val = in_use if (src, dst) in active_pips else False
 
             if not (in_use and not val):
+                if tile not in active_clks:
+                    active_clks[tile] = set()
+
+                active_clks[tile].add(src)
                 tags[tile][tag] = int(val)
 
+        for wire in wiredata[tile_type]:
+            if 'CLK' not in wire:
+                continue
+
+            if 'CLKFBOUT2IN' in wire:
+                continue
+
+            if 'CLKPLL' in wire:
+                continue
+
+            if 'CLKOUT' in wire:
+                continue
+
+            if tile not in active_wires:
+                active_wires[tile] = set()
+            segmk.add_tile_tag(
+                tile, '{}_ACTIVE'.format(wire), wire in active_wires[tile])
+
     # Output tags
     for tile, tile_tags in tags.items():
         for t, v in tile_tags.items():

fuzzers/034-cmt-pll-pips/generate.tcl

@@ -30,6 +30,23 @@ proc write_pip_txtdata {filename} {
     close $fp
 }
 
+proc write_used_wires {filename} {
+    puts "FUZ([pwd]): Writing $filename."
+
+    set fp [open $filename w]
+    set nets [get_nets -hierarchical]
+    set nnets [llength $nets]
+    set neti 0
+    foreach net $nets {
+        foreach node [get_nodes -of $net] {
+            foreach wire [get_wires -of $node] {
+                puts $fp "$wire"
+            }
+        }
+    }
+    close $fp
+}
+
 proc load_routes {filename} {
     puts "MANROUTE: Loading routes from $filename"
 
@@ -162,6 +179,7 @@ proc run {} {
     write_checkpoint -force design.dcp
     write_bitstream -force design.bit
     write_pip_txtdata design_pips.txt
+    write_used_wires design_wires.txt
 }
 
 run