mirror of https://github.com/openXC7/prjxray.git
Solve orphan INT columns in Kintex7.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman
parent
ebe9a457cd
commit
b04598da26
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@ -25,6 +25,7 @@ TILEGRID_TDB_DEPENDENCIES += mmcm/build/segbits_tilegrid.tdb
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endif
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ifeq (${XRAY_DATABASE}, kintex7)
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TILEGRID_TDB_DEPENDENCIES += orphan_int_column/build/segbits_tilegrid.tdb
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else
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# Disable DSP INT fuzzer on kintex7. It doesn't work, and isn't required.
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TILEGRID_TDB_DEPENDENCIES += dsp_int/build/segbits_tilegrid.tdb
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@ -92,6 +93,9 @@ fifo_int/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
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cfg_int/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
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cd cfg_int && $(MAKE)
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orphan_int_column/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
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cd orphan_int_column && $(MAKE)
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build/tilegrid_tdb.json: add_tdb.py $(TILEGRID_TDB_DEPENDENCIES)
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python3 add_tdb.py \
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--fn-in build/basicdb/tilegrid.json \
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@ -124,6 +128,7 @@ clean:
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cd monitor && $(MAKE) clean
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cd monitor_int && $(MAKE) clean
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cd cfg_int && $(MAKE) clean
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cd orphan_int_column && $(MAKE) clean
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.PHONY: database pushdb clean run
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@ -92,6 +92,9 @@ def run(fn_in, fn_out, verbose=False):
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("ps7_int/build/segbits_tilegrid.tdb", int_frames, int_words),
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("cfg_int/build/segbits_tilegrid.tdb", int_frames, int_words),
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("monitor_int/build/segbits_tilegrid.tdb", int_frames, int_words),
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(
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"orphan_int_column/build/segbits_tilegrid.tdb", int_frames,
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int_words),
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]
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for (tdb_fn, frames, words) in tdb_fns:
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@ -0,0 +1,3 @@
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N ?= 16
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GENERATE_ARGS?="--oneval 1 --design params.csv --dframe 9 --dword 0"
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include ../fuzzaddr/common.mk
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@ -0,0 +1,60 @@
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source "$::env(XRAY_DIR)/utils/utils.tcl"
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proc run {} {
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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write_pip_txtdata design.txt
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set fp [open top.txt]
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set int_tiles [split [read $fp] "\n"]
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close $fp
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set fp [open design.txt]
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set pips [split [read $fp] "\n"]
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close $fp
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set found_int_tiles {}
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foreach pip $pips {
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set parts [split $pip " "]
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set tile_idx [lsearch -exact $int_tiles [lindex $parts 0]]
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if {$tile_idx == -1} {
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continue
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}
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set tile [lindex $int_tiles $tile_idx]
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set pip_of_interest "$tile/INT_L.EL1END1->>EE2BEG1"
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if { $pip_of_interest == [lindex $parts 1] } {
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lappend found_int_tiles $tile
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}
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}
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set fp [open params.csv "w"]
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puts $fp "tile,val"
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foreach tile $int_tiles {
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if {$tile == ""} {
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continue
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}
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set pip_active [lsearch -exact $found_int_tiles $tile]
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if {$pip_active != -1} {
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puts $fp "$tile,1"
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} else {
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puts $fp "$tile,0"
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}
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}
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close $fp
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}
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run
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@ -0,0 +1,339 @@
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import os
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import random
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random.seed(int(os.getenv("SEED"), 16))
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from prjxray import util
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from prjxray.db import Database
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INT_TILE_TYPES = ['INT_L', 'INT_R']
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HCLK_TILE_TYPES = ['HCLK_L', 'HCLK_R', 'HCLK_L_BOT_UTURN', 'HCLK_R_BOT_UTURN']
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def get_int_column_roots(grid):
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for tile_name in sorted(grid.tiles()):
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loc = grid.loc_of_tilename(tile_name)
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gridinfo = grid.gridinfo_at_loc(loc)
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if gridinfo.tile_type not in INT_TILE_TYPES:
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continue
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next_gridinfo = grid.gridinfo_at_loc((loc.grid_x, loc.grid_y + 1))
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if next_gridinfo.tile_type in INT_TILE_TYPES:
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continue
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if next_gridinfo.tile_type in HCLK_TILE_TYPES:
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continue
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assert next_gridinfo.tile_type in [
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'B_TERM_INT', 'BRKH_INT', 'BRKH_B_TERM_INT'
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], next_gridinfo.tile_type
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yield tile_name
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def build_int_columns(grid):
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int_columns = {}
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for root_tile_name in get_int_column_roots(grid):
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assert root_tile_name not in int_columns
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int_columns[root_tile_name] = []
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tile_name = root_tile_name
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gridinfo = grid.gridinfo_at_tilename(tile_name)
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# Walk up INT column.
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while gridinfo.tile_type in INT_TILE_TYPES:
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int_columns[root_tile_name].append(tile_name)
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loc = grid.loc_of_tilename(tile_name)
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tile_name = grid.tilename_at_loc((loc.grid_x, loc.grid_y - 1))
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gridinfo = grid.gridinfo_at_tilename(tile_name)
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if gridinfo.tile_type in HCLK_TILE_TYPES:
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loc = grid.loc_of_tilename(tile_name)
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tile_name = grid.tilename_at_loc((loc.grid_x, loc.grid_y - 1))
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gridinfo = grid.gridinfo_at_tilename(tile_name)
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assert gridinfo.tile_type in [
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'T_TERM_INT', 'BRKH_INT', 'BRKH_TERM_INT'
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], gridinfo.tile_type
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return int_columns
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def pair_int_tiles(grid, int_tiles):
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tiles_left = set(int_tiles)
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while tiles_left:
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tile_name = tiles_left.pop()
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gridinfo = grid.gridinfo_at_tilename(tile_name)
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loc = grid.loc_of_tilename(tile_name)
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assert gridinfo.tile_type in INT_TILE_TYPES
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if gridinfo.tile_type == 'INT_L':
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other_int_tile = 'INT_R'
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other_loc = (loc.grid_x + 1, loc.grid_y)
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else:
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other_int_tile = 'INT_L'
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other_loc = (loc.grid_x - 1, loc.grid_y)
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paired_tile_name = grid.tilename_at_loc(other_loc)
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paired_gridinfo = grid.gridinfo_at_tilename(paired_tile_name)
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assert paired_gridinfo.tile_type == other_int_tile, paired_gridinfo.tile_type
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tiles_left.remove(paired_tile_name)
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yield sorted([tile_name, paired_tile_name])
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def is_orphan_int_row(grid, int_l, int_r):
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""" Returns true if given INT pair have no adjcent sites. """
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loc = grid.loc_of_tilename(int_l)
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if grid.gridinfo_at_loc(
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(loc.grid_x - 1, loc.grid_y)).tile_type != 'INT_INTERFACE_L':
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return False
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if grid.gridinfo_at_loc(
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(loc.grid_x - 2, loc.grid_y)).tile_type != 'VFRAME':
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return False
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loc = grid.loc_of_tilename(int_r)
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if grid.gridinfo_at_loc(
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(loc.grid_x + 1, loc.grid_y)).tile_type != 'INT_INTERFACE_R':
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return False
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if grid.gridinfo_at_loc(
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(loc.grid_x + 2,
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loc.grid_y)).tile_type not in ['CLK_FEED', 'CLK_BUFG_REBUF', 'NULL']:
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return False
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return True
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def gen_orphan_ints(grid):
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int_columns = build_int_columns(grid)
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for int_l_column, int_r_column in sorted(pair_int_tiles(
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grid, int_columns.keys())):
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found_site = False
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for int_l, int_r in zip(int_columns[int_l_column],
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int_columns[int_r_column]):
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if not is_orphan_int_row(grid, int_l, int_r):
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found_site = True
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break
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if not found_site:
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yield int_columns[int_l_column], int_columns[int_r_column]
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def write_params(params):
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pinstr = 'tile,val\n'
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for tile, (val) in sorted(params.items()):
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pinstr += '%s,%s\n' % (tile, val)
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open('params.csv', 'w').write(pinstr)
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def build_cross_int(params, grid, int_l, int_r):
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""" Toggles INT_R.ER1BEG1.EE4END0 """
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loc = grid.loc_of_tilename(int_r)
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origin_tile = grid.tilename_at_loc((loc.grid_x - 4, loc.grid_y))
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origin_gridinfo = grid.gridinfo_at_tilename(origin_tile)
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assert origin_gridinfo.tile_type == 'CLBLL_R'
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origin_site = sorted(origin_gridinfo.sites.keys())[random.randint(0, 1)]
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dest_tile = grid.tilename_at_loc((loc.grid_x + 4, loc.grid_y))
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dest_gridinfo = grid.gridinfo_at_tilename(dest_tile)
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assert dest_gridinfo.tile_type == 'CLBLL_L'
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dest_site = sorted(dest_gridinfo.sites.keys())[0]
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dest2_tile = grid.tilename_at_loc((loc.grid_x + 4, loc.grid_y + 1))
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dest2_gridinfo = grid.gridinfo_at_tilename(dest2_tile)
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assert dest2_gridinfo.tile_type == 'CLBLL_L', dest2_gridinfo.tile_type
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dest2_site = sorted(dest2_gridinfo.sites.keys())[1]
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if random.randint(0, 1):
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dest_wire = 'origin_wire_{origin_site}'.format(origin_site=origin_site)
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else:
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dest_wire = '1'
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if random.randint(0, 1):
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dest_wire2 = 'origin_wire_{origin_site}'.format(
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origin_site=origin_site)
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else:
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dest_wire2 = '1'
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if random.randint(0, 1):
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dest_wire3 = 'origin_wire_{origin_site}'.format(
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origin_site=origin_site)
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else:
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dest_wire3 = '1'
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if random.randint(0, 1):
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dest_wire4 = 'origin_wire_{origin_site}'.format(
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origin_site=origin_site)
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else:
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dest_wire4 = '1'
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# origin_site.AQ -> dest_tile.D6 enables INT_R.ER1BEG1.EE4END0
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print(
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"""
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// Force origin FF into A position with MUXF7_L and MUXF8
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wire origin_wire_{origin_site};
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wire f7_to_lo_{origin_site};
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wire lut_to_f7_{origin_site};
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(* KEEP, DONT_TOUCH, LOC = "{origin_site}" *)
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LUT6_L #(
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.INIT(0)
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) lut_rom_{origin_site} (
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.I0(1),
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.I1(origin_wire_{origin_site}),
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.I2(0),
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.I3(1),
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.I4(1),
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.I5(1),
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.LO(lut_to_f7_{origin_site})
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);
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(* KEEP, DONT_TOUCH, LOC = "{origin_site}" *)
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MUXF7_D f7_{origin_site} (
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.I0(lut_to_f7_{origin_site}),
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.LO(f7_to_lo_{origin_site}),
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.O(origin_wire_{origin_site})
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);
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(* KEEP, DONT_TOUCH, LOC = "{origin_site}" *)
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MUXF8 f8_{origin_site} (
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.I1(f7_to_lo_{origin_site})
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);
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wire dest_wire_{dest_site};
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wire dest_wire2_{dest_site};
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wire d_lut_to_f7_{dest_site}, f7_to_f8_{dest_site};
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// Force destination LUT into D position with MUXF7_L and MUXF8
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(* KEEP, DONT_TOUCH, LOC = "{dest_site}" *)
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LUT6_L #(
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.INIT(0)
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) d_lut_rom_{dest_site} (
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.I0(1),
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.I1(1),
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.I2(0),
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.I3(1),
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.I4(1),
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.I5(dest_wire_{dest_site}),
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.LO(d_lut_to_f7_{dest_site})
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);
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wire c_lut_to_f7_{dest_site};
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// Force destination LUT into C position with MUXF7_L and MUXF8
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(* KEEP, DONT_TOUCH, LOC = "{dest_site}" *)
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LUT6_L #(
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.INIT(0)
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) c_lut_rom_{dest_site} (
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.I0(1),
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.I1(1),
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.I2(0),
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.I3(1),
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.I4(1),
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.I5(dest_wire2_{dest_site}),
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.LO(c_lut_to_f7_{dest_site})
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);
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(* KEEP, DONT_TOUCH, LOC = "{dest_site}" *)
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MUXF7_L f7_{dest_site} (
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.I0(d_lut_to_f7_{dest_site}),
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.I1(c_lut_to_f7_{dest_site}),
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.LO(f7_to_f8_{dest_site})
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);
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(* KEEP, DONT_TOUCH, LOC = "{dest_site}" *)
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MUXF8 f8_{dest_site} (
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.I0(f7_to_f8_{dest_site})
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);
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assign dest_wire_{dest_site} = {dest_wire};
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assign dest_wire2_{dest_site} = {dest_wire2};
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wire dest_wire3_{dest_site2};
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wire dest_wire4_{dest_site2};
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wire lut_to_f7_{dest_site2}, f7_to_f8_{dest_site2};
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// Force destination LUT into D position with MUXF7_L and MUXF8
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(* KEEP, DONT_TOUCH, LOC = "{dest_site2}" *)
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LUT6_L #(
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.INIT(0)
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) d_lut_rom_{dest_site2} (
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.I0(dest_wire3_{dest_site2}),
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.I1(1),
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.I2(0),
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.I3(1),
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.I4(1),
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.I5(),
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.LO(lut_to_f7_{dest_site2})
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);
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// Force destination LUT into C position with MUXF7_L and MUXF8
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wire c_lut_to_f7_{dest_site2};
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(* KEEP, DONT_TOUCH, LOC = "{dest_site2}" *)
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LUT6_L #(
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.INIT(0)
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) c_lut_rom_{dest_site2} (
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.I0(dest_wire4_{dest_site2}),
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.I1(1),
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.I2(0),
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.I3(1),
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.I4(1),
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.I5(1),
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.LO(c_lut_to_f7_{dest_site2})
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);
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(* KEEP, DONT_TOUCH, LOC = "{dest_site2}" *)
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MUXF7_L f7_{dest_site2} (
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.I0(lut_to_f7_{dest_site2}),
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.I1(c_lut_to_f7_{dest_site2}),
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.LO(f7_to_f8_{dest_site2})
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);
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(* KEEP, DONT_TOUCH, LOC = "{dest_site2}" *)
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MUXF8 f8_{dest_site2} (
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.I0(f7_to_f8_{dest_site2})
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);
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assign dest_wire3_{dest_site2} = {dest_wire3};
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assign dest_wire4_{dest_site2} = {dest_wire4};
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""".format(
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dest_site=dest_site,
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dest_site2=dest2_site,
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origin_site=origin_site,
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dest_wire=dest_wire,
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dest_wire2=dest_wire2,
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dest_wire3=dest_wire3,
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dest_wire4=dest_wire4,
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))
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def run():
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print('''
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module top();
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''')
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int_tiles = []
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db = Database(util.get_db_root())
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grid = db.grid()
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params = {}
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for int_l_column, int_r_column in gen_orphan_ints(grid):
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for int_l, int_r in zip(int_l_column[1:6:2], int_r_column[1:6:2]):
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build_cross_int(params, grid, int_l, int_r)
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int_tiles.append(int_l)
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print("endmodule")
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with open('top.txt', 'w') as f:
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for tile in int_tiles:
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print(tile, file=f)
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if __name__ == '__main__':
|
||||
run()
|
||||
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Reference in New Issue