75e3d82a92
part: xc6slx150T
2022-03-03 15:37:18 +01:00
86fa1e01de
spiFlash: force subsector only for SST26VF032B
2022-02-26 19:10:18 +01:00
02e93ffec6
spiFlashdb: fix bp_offset list
2022-02-26 17:02:38 +01:00
add794ab67
spiFlashdb: add microchip SST26VF032B
2022-02-26 16:31:41 +01:00
aada7fe26b
spiFlash: when no subsector_erase compute end_addr with correct block size
2022-02-26 16:17:49 +01:00
655f2c61ec
spiFlash: add no block protect use case
2022-02-26 16:15:50 +01:00
3cfdfb1856
Update board.hpp
...
Use default cable. This is equivalent to 6MHz setting, albeit more versatile.
2022-02-21 23:05:37 -04:00
d4e8eef676
Add board and cable defaults for genesys2
2022-02-21 08:11:57 +00:00
52696309bb
spiFlashdb: spansion S25FL256S
2022-02-21 08:27:33 +01:00
7a7f1723ea
add support for colorlight-i9
2022-02-20 01:41:17 +01:00
6059c9dbfb
Remove the Tigard default cable, as the board does not have an on-board JTAG adapter.
2022-02-19 17:14:49 +10:30
7022e2101a
Add support for the QMTech Kintex7 Core Board
2022-02-19 14:22:55 +10:30
1cb85a5a21
Add support for the Spansion S25FL256L flash on the QMTech Kintex 7 board
2022-02-19 14:22:26 +10:30
905e96dfec
Add digilent_zybo_z7 10/20 support
2022-02-15 21:01:11 -08:00
5099b57ce3
Merge pull request #174 from tarikgraba/master
...
Add support for Terasic DE1-SoC board
2022-02-09 20:14:38 +01:00
56457a4023
Merge pull request #173 from rstephan/tables
...
Nicer layout for the boards/fpga/cables table
2022-02-09 18:17:35 +01:00
63c9ec01b7
Fixed right alignment problem.
2022-02-09 17:55:16 +01:00
5aa34c6364
board: add Terasic DE1-SoC board
2022-02-09 17:22:38 +01:00
d188314ae3
part: add altera 5CSEMA5 (cyclone V Soc)
2022-02-09 17:21:19 +01:00
a0ef85d516
display: use a less dark blue
2022-02-09 08:33:21 +01:00
687503673e
jtag: for unknown IDCODE display a more complete error
2022-02-09 08:32:41 +01:00
0a43d1b797
part: add map manufacturer id <-> name
2022-02-09 08:32:06 +01:00
12c5e6ba19
Nicer layout for the boards/fpga/cables table
2022-02-08 19:31:37 +01:00
498c01889f
spiFlash: fix overflow test ( #172 )
2022-02-07 07:44:11 +01:00
350570ad2d
board: add tangnano1k to board_list
2022-01-28 13:53:33 +02:00
977900954e
part: add GW1NZ-1
2022-01-27 22:55:21 +02:00
db407a4263
adding xilinx AC701 development kit
2022-01-26 16:42:03 +01:00
f30cca46d8
no dash for zedboard fpga name
2022-01-26 16:29:35 +01:00
0d1905425c
add board zc702 in board.hpp
2022-01-26 16:21:52 +01:00
b4ffe4bf66
xilinx: fix typo
2022-01-24 18:58:32 +01:00
acf677dd46
tangnano9k: new board, with the same cable w/ tangnano4k
...
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2022-01-22 20:51:05 +08:00
dc4a454b94
gowin: add support for GW1NR-9C
...
GW1NR-9C has a different idcode with GW1NR-9.
Add support for it by adding the idcode.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2022-01-22 20:49:35 +08:00
fb2aadadad
cable: adding Olimex ARM-USB-OCD-H
2022-01-20 19:37:50 +01:00
1ab454359f
ftdiJtagMPSSE,ftdipp_mpsse: fix verbose level -> must be an int8_t not uint8_t
2022-01-19 18:42:15 +01:00
5365a9f9cf
ice40: program_cram, add TN ref
2022-01-18 08:37:07 +01:00
eb462d2bec
main: bitstream default target depends on mode spi/jtag
2022-01-18 08:09:54 +01:00
60ba2b1ccc
ice40: add CRAM support
2022-01-18 08:08:48 +01:00
dbc6551a3c
part: add Kintex 160T
...
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2022-01-14 09:01:23 +01:00
ecc76baa97
board: alinx AXU2CGA
2022-01-13 08:55:26 +01:00
904bf46315
part: adding zynqmp xczu2cg idcode
2022-01-13 08:48:53 +01:00
f44f92ea4b
xilinx: adding zynqmp support and a method to init this family of devices
2022-01-13 08:41:38 +01:00
dddee79f53
jtag: adding method to inject device into active device list
2022-01-13 07:42:14 +01:00
1f59dfd671
jtag: improving jtag chain detection: now searching for masked and unmasked idcode
2022-01-13 07:34:00 +01:00
796483f61f
jtag: fix shiftIR: bypass_after must be computed in all case
2022-01-09 15:38:37 +01:00
ce7f4566c3
board: ulx3s_dfu
2021-12-24 18:10:22 +01:00
2c5a162cc4
dfu: add debug level, only print device open fails in debug mode
2021-12-24 15:48:16 +01:00
17a874fc04
main: fix SPI access
2021-12-24 11:19:30 +01:00
cbae44e1ee
ice40: flash reset powerup are done into spiFlash
2021-12-24 11:13:36 +01:00
39ed7ec7f1
colognechip: suppress warnings
2021-12-24 10:29:21 +01:00
310d21ebf5
dfu: when libusb_open fails: skip device instead of error and stop
2021-12-24 10:26:31 +01:00
35efeb3eee
dfu: check libusb_open return value in searchDFUDevices
2021-12-23 14:08:54 +01:00
f943a8d3f0
Merge branch 'master' of github.com:trabucayre/openFPGALoader
2021-12-23 10:29:59 +01:00
3244f2e92a
dfu: fix memory leak
2021-12-23 10:29:47 +01:00
4cab198915
colognechip integration: create CologneChip SPI object in dynamic fashion as well
2021-12-23 08:54:48 +01:00
0979194da2
dfu: force USB reset when download end in DFUIdle state
2021-12-23 07:22:06 +01:00
db92ea068c
main: add protection for all devices. Add CLI args
2021-12-22 19:12:33 +01:00
fefea9fe8e
board: generic FTDI SPI
2021-12-22 19:12:02 +01:00
45f7f72030
all devices: add support to (un)protect flash, implement pre/post flash access. Use new spiInterface methods
2021-12-22 19:11:35 +01:00
af14e9b518
ftdispi: pre/post flash access
2021-12-22 19:09:04 +01:00
ffa90fb6fb
ftdipp_mpsse: better verbose level
2021-12-22 19:08:44 +01:00
b25e2e0125
spiFlash: enable/disable protection. now handle correctly device with protection enabled
2021-12-22 19:07:00 +01:00
21b44fc22f
spiInterface.hpp: add constructor, (un)protect flash, and generic pre/post flash access methods
2021-12-22 19:05:21 +01:00
7e91d97828
device.hpp: add (un)protect flash methods
2021-12-22 19:03:57 +01:00
de2917428e
spiInterface: add common method to (un)protect, write and dump SPI flash content
2021-12-22 19:01:58 +01:00
55d5cba9fb
spiFlashdb: add spansion S25FL 064P/128P
2021-12-22 18:59:52 +01:00
50bdbde809
spiFlashdb: add micron N25Q32
2021-12-22 18:58:51 +01:00
5df1d9775d
spiFlashdb: add windbond w25q devices
2021-12-22 18:58:07 +01:00
b18191b0ba
spiFlashdb: fix tb_offset for ISSI devices
2021-12-22 18:57:34 +01:00
496e6678ec
spiFlashdb: introduce conf register for tb
2021-12-22 18:56:53 +01:00
56a1e0310d
board: add arty S7 50
2021-12-21 18:21:39 +01:00
03c7d7faad
arty A7 100t support
2021-12-21 07:02:48 +01:00
f3e9a9fa6d
digilent_arty_z7 10/20 support
2021-12-20 18:10:17 +01:00
ee7570b251
zynq xc7z010 support
2021-12-20 18:09:52 +01:00
e026aa28c7
Digilent arty s7 25
2021-12-19 17:35:23 +01:00
37abf105aa
xilinx: use gz file by default
2021-12-19 17:34:14 +01:00
648f5e8bdb
size_t is actually unsigned
2021-12-18 17:03:52 +03:00
bae403c3a9
efinix/titanium: add missing JTAG idcode
2021-12-14 09:16:08 +01:00
18349fb6e8
efinix: add support for Titanium Ti60 f225 dev kit
2021-12-13 22:13:29 +01:00
1c91928175
Merge branch 'master' into colognechip/gatemate
2021-12-13 10:18:41 +01:00
1e1b93c27a
colognechip integration: introduce waitCfgDone() and check for raw data
2021-12-12 15:34:25 +01:00
e252e713dd
colognechip integration: apply review remarks
...
* add missing #include <string>
* add comment to part.hpp why highest nibble should be kept
* remove _reverseOrder variable from colognechipCfgParser.{hpp,cpp}
* rename cfgDone() to to a more meaningfull waitCfgDone()
2021-12-12 11:55:10 +01:00
dd0d668d96
colognechip integration: update code style
2021-12-11 16:36:29 +01:00
e4971897d7
jtag: ckeck highest nibble to prevent confusion between Cologne Chip GateMate and Efinix Trion T4/T8 devices
2021-12-11 16:35:30 +01:00
bc610383cd
part: add support for Anlogic ELF2 EF2M45
...
Anlogic EF2M45 is a FPGA with a co-packaged 4Mbit SPI Flash, and the
JTAG interface is the same with EG4S20.
Add support for it by adding it to the part database.
SPI Flash programming and SRAM programming are both tested.
The support of EF2M45 is also documented in this commit.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2021-12-11 02:12:32 +08:00
d09e5da0ba
colognechip integration: initial commit
...
This commit adds support for the Cologne Chip GateMate FPGA series. Both
Evaluation Board and Programmer Cable are supported. Configurations can be
loaded into the FPGA with both devices via JTAG or SPI. In addition to
reading/writing data from/to flashes directly via SPI, this can also be done
via the built-in JTAG-SPI-bypass. A direct wiring between programming hardware
and flash is no longer necessary in this case.
Signed-off-by: Patrick Urban <patrick.urban@web.de>
2021-12-10 12:12:32 +01:00
e182a53659
dfu: don't check filename -> let configBitstreamParser to do check
2021-12-07 14:17:09 +01:00
dfed1d1799
configBitstreamParser: cleanup
2021-12-03 07:21:22 +01:00
9005b2880b
CMakeList/configBitstreamParser: add optional zlib-ng support. No zlibxx is required
2021-12-02 07:20:58 +01:00
7ceaab0126
spiOverJtag: add bitstream for ECP4CE15F23
2021-11-28 16:51:42 +01:00
49b6bc6ce3
device: check if it's a compressed file -> extract real extension
2021-11-26 07:35:03 +01:00
ac09ac9b96
Merge branch 'trabucayre:master' into master
2021-11-25 15:10:14 +00:00
8fc67762f6
merged
2021-11-25 15:09:38 +00:00
c06e920143
updated to set authentication mode
2021-11-25 14:59:37 +00:00
7fe0a5ab66
wip: adding pubkey programming
2021-11-25 14:50:33 +00:00
7e7e030661
wip: adding pubkey programming
2021-11-25 14:13:17 +00:00
7a19f94f19
add zlib support (currently limited to altera spiOverJtag)
2021-11-25 08:11:50 +01:00
70e9671b3a
device: if filename has no extension -> use raw type
2021-11-24 07:35:33 +01:00
533cd64f37
lattice: if unknown file type, fails only for SRAM
2021-11-24 07:35:10 +01:00
98a025d68e
lattice: improve message for idcode mismatch
2021-11-22 07:01:19 +01:00
9f4ed8aaf6
latticeBitParser: fix loop type
2021-11-20 18:36:09 +01:00
Gwenhael Goavec-Merou
Torsten Reuschel
jonathan kimmitt
Hirosh Dabui
Rod Whitby
Hansem Ro
Stephan Ruloff
TG
Verneri Hirvonen
Fabien Marteau
Icenowy Zheng
Karol Gugala
Patrick Urban
uis
Franck Jullien
abacomartin
Martin Beynon