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no dash for zedboard fpga name

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This commit is contained in:
Fabien Marteau
2022-01-26 16:29:35 +01:00
parent 99df282905
commit f30cca46d8
1 changed files with 2 additions and 2 deletions
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src/board.hpp
+2 -2
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@@ -116,7 +116,7 @@ static std::map <std::string, target_board_t> board_list = {
JTAG_BOARD("basys3", "xc7a35tcpg236", "digilent", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("nexysVideo", "xc7a200tsbg484", "digilent_b", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("kc705", "", "digilent", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("zc702", "xc7z020-clg484", "digilent", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("zc702", "xc7z020clg484", "digilent", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("colorlight", "", "", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("colorlight-i5", "", "cmsisdap", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("crosslinknx_evn", "", "ft2232", 0, 0, CABLE_DEFAULT),
@@ -177,7 +177,7 @@ static std::map <std::string, target_board_t> board_list = {
SPI_BOARD("titanium_ti60_f225","efinix", "efinix_spi_ft4232",
DBUS4, DBUS5, DBUS7, DBUS3, DBUS0, DBUS1, DBUS2, DBUS6, 0, CABLE_DEFAULT),
JTAG_BOARD("titanium_ti60_f225_jtag", "","efinix_jtag_ft4232", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("zedboard", "xc7z020-clg484", "digilent_hs2", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("zedboard", "xc7z020clg484", "digilent_hs2", 0, 0, CABLE_DEFAULT),
};
#endif