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arty A7 100t support

This commit is contained in:
Gwenhael Goavec-Merou 2021-12-21 07:02:48 +01:00
parent 3674406227
commit 03c7d7faad
2 changed files with 5 additions and 1 deletions
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3
doc/compatibility/board.rst
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@ -16,7 +16,8 @@ Boards
======================= ================================================================================================================================================= ============================= ========= ========
acornCle215 `Acorn CLE 215+ <http://squirrelsresearch.com/acorn-cle-215/>`__ Artix xc7a200tsbg484 OK OK
alchitry_au `Alchitry Au <https://alchitry.com/products/alchitry-au-fpga-development-board>`__ Artix xc7a35tftg256 OK OK
arty `Digilent Arty A7 <https://reference.digilentinc.com/reference/programmable-logic/arty-a7/start>`__ Artix xc7a35ticsg324 OK OK
arty_a7_35t `Digilent Arty A7 <https://reference.digilentinc.com/reference/programmable-logic/arty-a7/start>`__ Artix xc7a35ticsg324 OK OK
arty_a7_100t `Digilent Arty A7 <https://reference.digilentinc.com/reference/programmable-logic/arty-a7/start>`__ Artix xc7a100tcsg324 OK OK
arty_s7_25 `Digilent Arty S7 <https://reference.digilentinc.com/reference/programmable-logic/arty-s7/start>`__ Spartan7 xc7s25csga324 OK OK
arty_s7_50 `Digilent Arty S7 <https://reference.digilentinc.com/reference/programmable-logic/arty-s7/start>`__ Spartan7 xc7s50csga324 OK OK
arty_z7_10 `Digilent Arty S7 <https://reference.digilentinc.com/reference/programmable-logic/arty-z7/start>`__ Zynq7000 xc7z010csg400 OK NA

3
src/board.hpp
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@ -104,7 +104,10 @@ typedef struct {
static std::map <std::string, target_board_t> board_list = {
JTAG_BOARD("acornCle215", "xc7a200tsbg484", "", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("alchitry_au", "xc7a35tftg256", "ft2232", 0, 0, CABLE_DEFAULT),
/* left for backward compatibility, use right name instead */
JTAG_BOARD("arty", "xc7a35tcsg324", "digilent", 0, 0, CABLE_MHZ(10)),
JTAG_BOARD("arty_a7_35t", "xc7a35tcsg324", "digilent", 0, 0, CABLE_MHZ(10)),
JTAG_BOARD("arty_a7_100t", "xc7a100tcsg324", "digilent", 0, 0, CABLE_MHZ(10)),
JTAG_BOARD("arty_s7_25", "xc7s25csga324", "digilent", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("arty_z7_10", "xc7z010clg400", "digilent", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("arty_z7_20", "xc7z020clg400", "digilent", 0, 0, CABLE_DEFAULT),