adding xilinx AC701 development kit

doc/boards.yml

@@ -1,3 +1,10 @@
+- ID: ac701
+  Description: Xilinx Artix-7 FPGA AC701 Evaluation Kit
+  URL: https://www.xilinx.com/products/boards-and-kits/ek-a7-ac701-g.html
+  FPGA: Artix xc7a200t2fbg676c
+  Memory: OK
+  Flash: NT
+
 - ID: acornCle215
   Description: Acorn CLE 215+
   URL: http://squirrelsresearch.com/acorn-cle-215

src/board.hpp

@@ -102,6 +102,7 @@ typedef struct {
 	{_name, {"", _cable, _fpga_part, 0, 0, 0, COMM_DFU, {}, {}, 0, _vid, _pid, _alt}}
 
 static std::map <std::string, target_board_t> board_list = {
+	JTAG_BOARD("ac701",           "xc7a200t2fbg676c", "digilent", 0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("acornCle215",     "xc7a200tsbg484", "",         0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("alchitry_au",     "xc7a35tftg256",  "ft2232",   0, 0, CABLE_DEFAULT),
 	/* left for backward compatibility, use right name instead */