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openFPGALoader
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910 Commits 21 Branches 23 Tags 15 MiB
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527 Commits

Author SHA1 Message Date
Gwenhael Goavec-Merou 259914910f board: Xilinx ZC706 2022-03-10 18:53:41 +01:00
Gwenhael Goavec-Merou 6ba1968952 part: Zynq XC7Z045 2022-03-10 18:53:12 +01:00
Gwenhael Goavec-Merou 74eb812c6d cable: digilent jtag-smt2-nc 2022-03-10 18:52:47 +01:00
Gwenhael Goavec-Merou 2eac30c24e ftdiJtagMPSSE: fix read/write polarity: always write on neg, read is by default on pos but may on neg with arty 2022-03-10 07:43:14 +01:00
Gwenhael Goavec-Merou 28ebc98b1b board: add CERN SPEC150 2022-03-03 15:40:42 +01:00
Gwenhael Goavec-Merou 75e3d82a92 part: xc6slx150T 2022-03-03 15:37:18 +01:00
Gwenhael Goavec-Merou 86fa1e01de spiFlash: force subsector only for SST26VF032B 2022-02-26 19:10:18 +01:00
Gwenhael Goavec-Merou 02e93ffec6 spiFlashdb: fix bp_offset list 2022-02-26 17:02:38 +01:00
Gwenhael Goavec-Merou add794ab67 spiFlashdb: add microchip SST26VF032B 2022-02-26 16:31:41 +01:00
Gwenhael Goavec-Merou aada7fe26b spiFlash: when no subsector_erase compute end_addr with correct block size 2022-02-26 16:17:49 +01:00
Gwenhael Goavec-Merou 655f2c61ec spiFlash: add no block protect use case 2022-02-26 16:15:50 +01:00
Torsten Reuschel 3cfdfb1856
Update board.hpp 
Use default cable. This is equivalent to 6MHz setting, albeit more versatile.
 2022-02-21 23:05:37 -04:00
jonathan kimmitt d4e8eef676 Add board and cable defaults for genesys2 2022-02-21 08:11:57 +00:00
Gwenhael Goavec-Merou 52696309bb spiFlashdb: spansion S25FL256S 2022-02-21 08:27:33 +01:00
Hirosh Dabui 7a7f1723ea add support for colorlight-i9 2022-02-20 01:41:17 +01:00
Rod Whitby 6059c9dbfb Remove the Tigard default cable, as the board does not have an on-board JTAG adapter. 2022-02-19 17:14:49 +10:30
Rod Whitby 7022e2101a Add support for the QMTech Kintex7 Core Board 2022-02-19 14:22:55 +10:30
Rod Whitby 1cb85a5a21 Add support for the Spansion S25FL256L flash on the QMTech Kintex 7 board 2022-02-19 14:22:26 +10:30
Hansem Ro 905e96dfec Add digilent_zybo_z7 10/20 support 2022-02-15 21:01:11 -08:00
Gwenhael Goavec-Merou 5099b57ce3
Merge pull request #174 from tarikgraba/master 
Add support  for Terasic DE1-SoC board
 2022-02-09 20:14:38 +01:00
Gwenhael Goavec-Merou 56457a4023
Merge pull request #173 from rstephan/tables 
Nicer layout for the boards/fpga/cables table
 2022-02-09 18:17:35 +01:00
Stephan Ruloff 63c9ec01b7 Fixed right alignment problem. 2022-02-09 17:55:16 +01:00
TG 5aa34c6364 board: add Terasic DE1-SoC board 2022-02-09 17:22:38 +01:00
TG d188314ae3 part: add altera 5CSEMA5 (cyclone V Soc) 2022-02-09 17:21:19 +01:00
Gwenhael Goavec-Merou a0ef85d516 display: use a less dark blue 2022-02-09 08:33:21 +01:00
Gwenhael Goavec-Merou 687503673e jtag: for unknown IDCODE display a more complete error 2022-02-09 08:32:41 +01:00
Gwenhael Goavec-Merou 0a43d1b797 part: add map manufacturer id <-> name 2022-02-09 08:32:06 +01:00
Stephan Ruloff 12c5e6ba19 Nicer layout for the boards/fpga/cables table 2022-02-08 19:31:37 +01:00
Gwenhael Goavec-Merou 498c01889f spiFlash: fix overflow test (#172) 2022-02-07 07:44:11 +01:00
Verneri Hirvonen 350570ad2d board: add tangnano1k to board_list 2022-01-28 13:53:33 +02:00
Verneri Hirvonen 977900954e part: add GW1NZ-1 2022-01-27 22:55:21 +02:00
Fabien Marteau db407a4263 adding xilinx AC701 development kit 2022-01-26 16:42:03 +01:00
Fabien Marteau f30cca46d8 no dash for zedboard fpga name 2022-01-26 16:29:35 +01:00
Fabien Marteau 0d1905425c add board zc702 in board.hpp 2022-01-26 16:21:52 +01:00
Gwenhael Goavec-Merou b4ffe4bf66 xilinx: fix typo 2022-01-24 18:58:32 +01:00
Icenowy Zheng acf677dd46 tangnano9k: new board, with the same cable w/ tangnano4k 
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
 2022-01-22 20:51:05 +08:00
Icenowy Zheng dc4a454b94 gowin: add support for GW1NR-9C 
GW1NR-9C has a different idcode with GW1NR-9.

Add support for it by adding the idcode.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
 2022-01-22 20:49:35 +08:00
Gwenhael Goavec-Merou fb2aadadad cable: adding Olimex ARM-USB-OCD-H 2022-01-20 19:37:50 +01:00
Gwenhael Goavec-Merou 1ab454359f ftdiJtagMPSSE,ftdipp_mpsse: fix verbose level -> must be an int8_t not uint8_t 2022-01-19 18:42:15 +01:00
Gwenhael Goavec-Merou 5365a9f9cf ice40: program_cram, add TN ref 2022-01-18 08:37:07 +01:00
Gwenhael Goavec-Merou eb462d2bec main: bitstream default target depends on mode spi/jtag 2022-01-18 08:09:54 +01:00
Gwenhael Goavec-Merou 60ba2b1ccc ice40: add CRAM support 2022-01-18 08:08:48 +01:00
Karol Gugala dbc6551a3c part: add Kintex 160T 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2022-01-14 09:01:23 +01:00
Gwenhael Goavec-Merou ecc76baa97 board: alinx AXU2CGA 2022-01-13 08:55:26 +01:00
Gwenhael Goavec-Merou 904bf46315 part: adding zynqmp xczu2cg idcode 2022-01-13 08:48:53 +01:00
Gwenhael Goavec-Merou f44f92ea4b xilinx: adding zynqmp support and a method to init this family of devices 2022-01-13 08:41:38 +01:00
Gwenhael Goavec-Merou dddee79f53 jtag: adding method to inject device into active device list 2022-01-13 07:42:14 +01:00
Gwenhael Goavec-Merou 1f59dfd671 jtag: improving jtag chain detection: now searching for masked and unmasked idcode 2022-01-13 07:34:00 +01:00
Gwenhael Goavec-Merou 796483f61f jtag: fix shiftIR: bypass_after must be computed in all case 2022-01-09 15:38:37 +01:00
Gwenhael Goavec-Merou ce7f4566c3 board: ulx3s_dfu 2021-12-24 18:10:22 +01:00