2021-06-26 15:24:07 +02:00
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// SPDX-License-Identifier: Apache-2.0
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/*
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* Copyright (C) 2019 Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
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*/
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2019-09-26 18:29:20 +02:00
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#ifndef BOARD_HPP
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#define BOARD_HPP
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#include <map>
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2020-03-07 11:00:29 +01:00
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#include "cable.hpp"
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/* AN_232R-01_Bit_Bang_Mode_Available_For_FT232R_and_Ft245R */
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enum {
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2022-08-23 18:37:43 +02:00
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FT232RL_TXD = 0,
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FT232RL_RXD = 1,
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FT232RL_RTS = 2,
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FT232RL_CTS = 3,
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FT232RL_DTR = 4,
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FT232RL_DSR = 5,
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FT232RL_DCD = 6,
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FT232RL_RI = 7
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2020-10-31 08:40:18 +01:00
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};
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/* AN_108_Command_Processor_for_MPSSE_and_MCU_Host_Bus_Emulation_Modes */
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enum {
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2020-10-31 10:44:14 +01:00
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DBUS0 = (1 << 0),
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DBUS1 = (1 << 1),
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DBUS2 = (1 << 2),
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DBUS3 = (1 << 3),
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DBUS4 = (1 << 4),
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DBUS5 = (1 << 5),
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DBUS6 = (1 << 6),
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DBUS7 = (1 << 7),
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CBUS0 = (1 << 8),
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CBUS1 = (1 << 9),
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CBUS2 = (1 << 10),
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CBUS3 = (1 << 11),
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CBUS4 = (1 << 12),
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CBUS5 = (1 << 13),
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CBUS6 = (1 << 14),
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CBUS7 = (1 << 15)
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2020-03-07 11:00:29 +01:00
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};
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/*!
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2020-10-31 08:40:18 +01:00
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* \brief for bitbang mode this structure provide value for each JTAG signals
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2020-03-07 11:00:29 +01:00
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*/
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typedef struct {
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2020-10-31 08:40:18 +01:00
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uint8_t tms_pin; /*! TMS pin value */
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uint8_t tck_pin; /*! TCK pin value */
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uint8_t tdi_pin; /*! TDI pin value */
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uint8_t tdo_pin; /*! TDO pin value */
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2020-03-07 11:00:29 +01:00
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} jtag_pins_conf_t;
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2020-10-30 08:23:49 +01:00
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typedef struct {
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2020-10-31 08:40:18 +01:00
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uint16_t cs_pin; /*! CS pin value */
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uint16_t sck_pin; /*! SCK pin value */
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uint16_t miso_pin; /*! MISO pin value */
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uint16_t mosi_pin; /*! MOSI pin value */
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uint16_t holdn_pin; /*! HOLDN pin value */
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uint16_t wpn_pin; /*! WPN pin value */
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2020-10-30 08:23:49 +01:00
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} spi_pins_conf_t;
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2020-10-31 08:40:18 +01:00
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enum {
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COMM_JTAG = (1 << 0),
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2021-06-20 10:25:49 +02:00
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COMM_SPI = (1 << 1),
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COMM_DFU = (1 << 2),
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2020-10-31 08:40:18 +01:00
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};
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2020-03-07 11:00:29 +01:00
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/*!
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2022-12-18 13:56:54 +01:00
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* \brief a board has a target cable and optionally a pin configuration
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2020-03-07 11:00:29 +01:00
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* (bitbang mode)
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*/
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typedef struct {
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2020-10-31 08:40:18 +01:00
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std::string manufacturer;
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2020-03-07 11:00:29 +01:00
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std::string cable_name; /*! provide name of one entry in cable_list */
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2021-04-19 21:17:08 +02:00
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std::string fpga_part; /*! provide full fpga model name with package */
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2020-10-31 10:43:45 +01:00
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uint16_t reset_pin; /*! reset pin value */
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uint16_t done_pin; /*! done pin value */
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2021-10-23 08:44:23 +02:00
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uint16_t oe_pin; /*! output enable pin value */
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2020-10-31 10:43:45 +01:00
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uint16_t mode; /*! communication type (JTAG or SPI) */
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2020-10-31 08:40:18 +01:00
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jtag_pins_conf_t jtag_pins_config; /*! for bitbang, provide struct with pins value */
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spi_pins_conf_t spi_pins_config; /*! for SPI, provide struct with pins value */
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2021-07-11 16:20:15 +02:00
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uint32_t default_freq; /* Default clock speed: 0 = use cable default */
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2021-07-17 08:34:44 +02:00
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uint16_t vid; /* optional VID: used only with DFU */
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uint16_t pid; /* optional VID: used only with DFU */
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2021-10-03 18:31:55 +02:00
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int16_t altsetting; /* optional altsetting: used only with DFU */
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2021-04-19 21:17:08 +02:00
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} target_board_t;
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2020-03-07 11:00:29 +01:00
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2021-07-11 16:20:15 +02:00
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#define CABLE_DEFAULT 0
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#define CABLE_MHZ(_m) ((_m) * 1000000)
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#define JTAG_BOARD(_name, _fpga_part, _cable, _rst, _done, _freq) \
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2021-10-23 08:44:23 +02:00
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{_name, {"", _cable, _fpga_part, _rst, _done, 0, COMM_JTAG, {}, {}, _freq, 0, 0, -1}}
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2021-07-14 08:05:36 +02:00
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#define JTAG_BITBANG_BOARD(_name, _fpga_part, _cable, _rst, _done, _tms, _tck, _tdi, _tdo, _freq) \
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2021-10-23 08:44:23 +02:00
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{_name, {"", _cable, _fpga_part, _rst, _done, 0, COMM_JTAG, { _tms, _tck, _tdi, _tdo }, {}, \
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2021-10-03 18:31:55 +02:00
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_freq, 0, 0, -1}}
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2021-10-23 08:44:23 +02:00
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#define SPI_BOARD(_name, _manufacturer, _cable, _rst, _done, _oe, _cs, _sck, _si, _so, _holdn, _wpn, _freq) \
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{_name, {_manufacturer, _cable, "", _rst, _done, _oe, COMM_SPI, {}, \
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2021-10-03 18:31:55 +02:00
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{_cs, _sck, _so, _si, _holdn, _wpn}, _freq, 0, 0, -1}}
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2021-10-03 12:39:06 +02:00
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#define DFU_BOARD(_name, _fpga_part, _cable, _vid, _pid, _alt) \
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2021-10-23 08:44:23 +02:00
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{_name, {"", _cable, _fpga_part, 0, 0, 0, COMM_DFU, {}, {}, 0, _vid, _pid, _alt}}
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2020-10-31 08:04:43 +01:00
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2021-04-19 21:17:08 +02:00
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static std::map <std::string, target_board_t> board_list = {
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2022-01-26 16:42:03 +01:00
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JTAG_BOARD("ac701", "xc7a200t2fbg676c", "digilent", 0, 0, CABLE_DEFAULT),
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2021-07-11 16:20:15 +02:00
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JTAG_BOARD("acornCle215", "xc7a200tsbg484", "", 0, 0, CABLE_DEFAULT),
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2023-01-04 19:00:08 +01:00
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JTAG_BOARD("analogMax", "", "ft2232", 0, 0, CABLE_DEFAULT),
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2022-12-11 20:39:32 +01:00
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JTAG_BOARD("litex-acorn-baseboard-mini", "xc7a200tsbg484", "", 0, 0, CABLE_DEFAULT),
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2021-07-11 16:20:15 +02:00
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JTAG_BOARD("alchitry_au", "xc7a35tftg256", "ft2232", 0, 0, CABLE_DEFAULT),
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2022-10-30 14:05:22 +01:00
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JTAG_BOARD("alchitry_au_plus","xc7a100tftg256", "ft2232", 0, 0, CABLE_DEFAULT),
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2023-02-09 21:49:03 +01:00
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JTAG_BOARD("alinx_ax516", "xc6slx16csg324", "", 0, 0, CABLE_DEFAULT),
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2021-12-21 07:02:48 +01:00
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/* left for backward compatibility, use right name instead */
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2021-07-11 16:20:15 +02:00
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JTAG_BOARD("arty", "xc7a35tcsg324", "digilent", 0, 0, CABLE_MHZ(10)),
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2021-12-21 07:02:48 +01:00
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JTAG_BOARD("arty_a7_35t", "xc7a35tcsg324", "digilent", 0, 0, CABLE_MHZ(10)),
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JTAG_BOARD("arty_a7_100t", "xc7a100tcsg324", "digilent", 0, 0, CABLE_MHZ(10)),
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2021-12-19 17:35:23 +01:00
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JTAG_BOARD("arty_s7_25", "xc7s25csga324", "digilent", 0, 0, CABLE_DEFAULT),
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2021-12-21 18:21:39 +01:00
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JTAG_BOARD("arty_s7_50", "xc7s50csga324", "digilent", 0, 0, CABLE_DEFAULT),
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2021-12-20 18:10:17 +01:00
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JTAG_BOARD("arty_z7_10", "xc7z010clg400", "digilent", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("arty_z7_20", "xc7z020clg400", "digilent", 0, 0, CABLE_DEFAULT),
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2022-01-13 08:55:26 +01:00
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JTAG_BOARD("axu2cga", "xczu2cg", "", 0, 0, CABLE_DEFAULT),
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2021-07-11 16:20:15 +02:00
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JTAG_BOARD("basys3", "xc7a35tcpg236", "digilent", 0, 0, CABLE_DEFAULT),
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2023-01-29 15:35:47 +01:00
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JTAG_BOARD("c5g", "", "usb-blaster",0, 0, CABLE_DEFAULT),
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2022-09-30 11:01:49 +02:00
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JTAG_BOARD("cmod_s7", "xc7s25csga225", "digilent", 0, 0, CABLE_DEFAULT),
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2022-09-30 21:17:45 +02:00
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JTAG_BOARD("cmoda7_35t", "xc7a35tcpg236", "digilent", 0, 0, CABLE_DEFAULT),
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2021-07-11 16:20:15 +02:00
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JTAG_BOARD("colorlight", "", "", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("colorlight-i5", "", "cmsisdap", 0, 0, CABLE_DEFAULT),
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2022-02-20 01:41:17 +01:00
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JTAG_BOARD("colorlight-i9", "", "cmsisdap", 0, 0, CABLE_DEFAULT),
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2021-07-11 16:20:15 +02:00
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JTAG_BOARD("crosslinknx_evn", "", "ft2232", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("cyc1000", "10cl025256", "ft2232", 0, 0, CABLE_DEFAULT),
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2022-12-25 22:53:45 +01:00
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JTAG_BOARD("c10lp-refkit", "10cl055484", "ft2232", 0, 0, CABLE_DEFAULT),
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2021-07-11 16:20:15 +02:00
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JTAG_BOARD("de0", "", "usb-blaster",0, 0, CABLE_DEFAULT),
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JTAG_BOARD("de0nano", "ep4ce2217", "usb-blaster",0, 0, CABLE_DEFAULT),
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JTAG_BOARD("de0nanoSoc", "", "usb-blasterII",0, 0, CABLE_DEFAULT),
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2023-01-09 22:52:54 +01:00
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JTAG_BOARD("de10lite", "", "usb-blaster",0, 0, CABLE_DEFAULT),
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2021-07-11 16:20:15 +02:00
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JTAG_BOARD("de10nano", "", "usb-blasterII",0, 0, CABLE_DEFAULT),
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2022-02-09 17:22:38 +01:00
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JTAG_BOARD("de1Soc", "5CSEMA5", "usb-blasterII",0, 0, CABLE_DEFAULT),
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2023-01-04 20:11:21 +01:00
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JTAG_BOARD("deca", "10M50DA", "usb-blasterII",0, 0, CABLE_DEFAULT),
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2021-07-11 16:20:15 +02:00
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JTAG_BOARD("ecp5_evn", "", "ft2232", 0, 0, CABLE_DEFAULT),
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2023-02-09 21:49:03 +01:00
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JTAG_BOARD("ecpix5", "", "ecpix5-debug", 0, 0, CABLE_DEFAULT),
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2021-04-19 21:17:08 +02:00
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SPI_BOARD("fireant", "efinix", "ft232",
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2021-10-23 08:44:23 +02:00
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DBUS4, DBUS5, 0, DBUS3, DBUS0, DBUS1, DBUS2, DBUS6, 0, CABLE_DEFAULT),
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2021-10-03 12:39:06 +02:00
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DFU_BOARD("fomu", "", "dfu", 0x1209, 0x5bf0, 0),
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2023-02-09 21:49:03 +01:00
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SPI_BOARD("ft2232_spi", "none", "ft2232",
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DBUS7, DBUS6, 0,
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DBUS4, DBUS0, DBUS1, DBUS2,
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0, 0, CABLE_DEFAULT),
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2021-12-10 12:12:32 +01:00
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SPI_BOARD("gatemate_pgm_spi", "colognechip", "gatemate_pgm",
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DBUS4, DBUS5, CBUS0, DBUS3, DBUS0, DBUS1, DBUS2, 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("gatemate_evb_jtag", "", "gatemate_evb_jtag", 0, 0, CABLE_DEFAULT),
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SPI_BOARD("gatemate_evb_spi", "colognechip", "gatemate_evb_spi",
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DBUS4, DBUS5, CBUS0, DBUS3, DBUS0, DBUS1, DBUS2, 0, 0, CABLE_DEFAULT),
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2023-02-09 21:49:03 +01:00
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JTAG_BOARD("genesys2", "xc7k325tffg900", "digilent_b", 0, 0, CABLE_DEFAULT),
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2023-03-04 17:55:02 +01:00
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JTAG_BOARD("hseda-xc6slx16", "xc6slx16ftg256", "", 0, 0, CABLE_DEFAULT),
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2020-10-31 15:02:54 +01:00
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/* most ice40 boards uses the same pinout */
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2021-04-19 21:17:08 +02:00
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SPI_BOARD("ice40_generic", "lattice", "ft2232",
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2021-10-23 08:44:23 +02:00
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DBUS7, DBUS6, 0,
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2020-10-31 15:02:54 +01:00
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DBUS4, DBUS0, DBUS1, DBUS2,
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2021-07-14 08:05:36 +02:00
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0, 0, CABLE_DEFAULT),
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2021-10-03 12:42:35 +02:00
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DFU_BOARD("icebreaker-bitsy", "", "dfu", 0x1d50, 0x6146, 0),
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2023-02-09 21:49:03 +01:00
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JTAG_BOARD("kc705", "", "digilent", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("LD-SCHOKO", "LFE5U-45F-6CABGA256", "", 0, 0, CABLE_MHZ(6)),
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DFU_BOARD("LD-SCHOKO", "", "dfu", 0x16d0, 0x116d, 0),
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JTAG_BOARD("LD-KONFEKT", "LFE5U-12F-6BG256C", "", 0, 0, CABLE_MHZ(6)),
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DFU_BOARD("LD-KONFEKT", "", "dfu", 0x16d0, 0x116d, 0),
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2021-07-11 16:20:15 +02:00
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JTAG_BOARD("licheeTang", "", "anlogicCable", 0, 0, CABLE_DEFAULT),
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2021-01-25 18:52:54 +01:00
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/* left for backward compatibility, use tec0117 instead */
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2021-07-11 16:20:15 +02:00
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JTAG_BOARD("littleBee", "", "ft2232", 0, 0, CABLE_DEFAULT),
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2023-02-09 21:49:03 +01:00
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JTAG_BOARD("machXO2EVN", "", "ft2232", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("machXO3SK", "", "ft2232", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("machXO3EVN", "", "ft2232", 0, 0, CABLE_DEFAULT),
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2021-07-11 16:20:15 +02:00
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JTAG_BOARD("minispartan6", "", "ft2232", 0, 0, CABLE_DEFAULT),
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2023-02-09 21:49:03 +01:00
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JTAG_BOARD("nexys_a7_50", "xc7a50tcsg324", "digilent", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("nexys_a7_100", "xc7a100tcsg324", "digilent", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("nexysVideo", "xc7a200tsbg484", "digilent_b", 0, 0, CABLE_DEFAULT),
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2021-10-03 12:39:06 +02:00
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DFU_BOARD("orangeCrab", "", "dfu", 0x1209, 0x5af0, 0),
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2023-02-09 21:49:03 +01:00
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DFU_BOARD("orbtrace_dfu", "", "dfu", 0x1209, 0x3442, 1),
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JTAG_BOARD("papilio_one", "xc3s500evq100", "papilio", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("pipistrello", "xc6slx45csg324", "ft2232", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("pynq_z2", "xc7z020clg400", "ft2232", 0, 0, CABLE_DEFAULT),
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2021-11-28 16:50:13 +01:00
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JTAG_BOARD("qmtechCycloneIV", "ep4ce1523", "", 0, 0, CABLE_DEFAULT),
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2021-07-11 16:20:15 +02:00
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JTAG_BOARD("qmtechCycloneV", "5ce223", "", 0, 0, CABLE_DEFAULT),
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2022-03-13 14:14:52 +01:00
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JTAG_BOARD("qmtechCycloneV_5ce523", "5ce523", "", 0,0, CABLE_DEFAULT),
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2022-02-19 07:44:49 +01:00
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JTAG_BOARD("qmtechKintex7", "xc7k325tffg676", "", 0, 0, CABLE_DEFAULT),
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2023-02-09 21:49:03 +01:00
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JTAG_BOARD("runber", "", "ft232", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("spartanEdgeAccelBoard", "", "",0, 0, CABLE_DEFAULT),
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2022-03-03 15:40:42 +01:00
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JTAG_BOARD("spec150", "xc6slx150tfgg484", "", 0, 0, CABLE_DEFAULT),
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2023-01-06 08:22:43 +01:00
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JTAG_BOARD("stlv7325", "xc7k325tffg676", "ft4232", 0, 0, CABLE_MHZ(3)),
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2021-11-06 10:33:25 +01:00
|
|
|
JTAG_BOARD("tangnano", "", "ch552_jtag", 0, 0, CABLE_DEFAULT),
|
2022-01-28 12:53:33 +01:00
|
|
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JTAG_BOARD("tangnano1k", "", "ft2232", 0, 0, CABLE_DEFAULT),
|
2021-09-02 13:54:34 +02:00
|
|
|
JTAG_BOARD("tangnano4k", "", "ft2232", 0, 0, CABLE_DEFAULT),
|
2022-01-22 13:51:05 +01:00
|
|
|
JTAG_BOARD("tangnano9k", "", "ft2232", 0, 0, CABLE_DEFAULT),
|
2022-07-26 20:25:02 +02:00
|
|
|
JTAG_BOARD("tangprimer20k", "", "ft2232", 0, 0, CABLE_DEFAULT),
|
2021-07-11 16:20:15 +02:00
|
|
|
JTAG_BOARD("tec0117", "", "ft2232", 0, 0, CABLE_DEFAULT),
|
2023-02-09 21:49:03 +01:00
|
|
|
SPI_BOARD("titanium_ti60_f225","efinix", "efinix_spi_ft4232",
|
|
|
|
|
DBUS4, DBUS5, DBUS7, DBUS3, DBUS0, DBUS1, DBUS2, DBUS6, 0, CABLE_DEFAULT),
|
|
|
|
|
JTAG_BOARD("titanium_ti60_f225_jtag", "","efinix_jtag_ft4232", 0, 0, CABLE_DEFAULT),
|
|
|
|
|
SPI_BOARD("trion_t120_bga576","efinix", "efinix_spi_ft2232",
|
|
|
|
|
DBUS4, DBUS5, DBUS7, DBUS3, DBUS0, DBUS1, DBUS2, DBUS6, 0, CABLE_DEFAULT),
|
|
|
|
|
JTAG_BOARD("trion_t120_bga576_jtag", "", "ft2232_b", 0, 0, CABLE_DEFAULT),
|
2021-07-14 08:05:36 +02:00
|
|
|
JTAG_BITBANG_BOARD("ulx2s", "", "ft232RL", 0, 0,
|
|
|
|
|
FT232RL_RI, FT232RL_DSR, FT232RL_CTS, FT232RL_DCD, CABLE_DEFAULT),
|
|
|
|
|
JTAG_BITBANG_BOARD("ulx3s", "", "ft231X", 0, 0,
|
|
|
|
|
FT232RL_DCD, FT232RL_DSR, FT232RL_RI, FT232RL_CTS, CABLE_DEFAULT),
|
2021-12-24 18:10:22 +01:00
|
|
|
DFU_BOARD("ulx3s_dfu", "", "dfu", 0x1d50, 0x614b, 0),
|
2023-02-09 21:49:03 +01:00
|
|
|
JTAG_BOARD("usrpx300", "xc7k325tffg900", "digilent", 0, 0, CABLE_MHZ(15)),
|
|
|
|
|
JTAG_BOARD("usrpx310", "xc7k410tffg900", "digilent", 0, 0, CABLE_MHZ(15)),
|
|
|
|
|
JTAG_BOARD("vcu118", "xcvu9p-flga2104", "jtag-smt2-nc", 0, 0, CABLE_DEFAULT),
|
2023-02-19 11:38:15 +01:00
|
|
|
JTAG_BOARD("vcu128", "xcvu37p-fsvh2892", "ft4232", 0, 0, CABLE_DEFAULT),
|
2023-02-28 22:40:41 +01:00
|
|
|
JTAG_BOARD("xem8320", "xcau25p-2ffvb676", "" , 0, 0, CABLE_DEFAULT),
|
2023-04-19 06:58:39 +02:00
|
|
|
JTAG_BOARD("xyloni_jtag", "t8f81", "efinix_jtag_ft4232", 0, 0, CABLE_DEFAULT),
|
2021-10-15 09:17:59 +02:00
|
|
|
SPI_BOARD("xyloni_spi", "efinix", "efinix_spi_ft4232",
|
2021-10-23 08:44:23 +02:00
|
|
|
DBUS4, DBUS5, DBUS7, DBUS3, DBUS0, DBUS1, DBUS2, DBUS6, 0, CABLE_DEFAULT),
|
2023-02-09 21:49:03 +01:00
|
|
|
JTAG_BOARD("xtrx", "xc7a50tcpg236", "" , 0, 0, CABLE_DEFAULT),
|
|
|
|
|
JTAG_BOARD("zc702", "xc7z020clg484", "digilent", 0, 0, CABLE_DEFAULT),
|
2022-03-10 18:53:41 +01:00
|
|
|
JTAG_BOARD("zc706", "xc7z045ffg900", "jtag-smt2-nc", 0, 0, CABLE_DEFAULT),
|
2022-03-19 10:08:51 +01:00
|
|
|
JTAG_BOARD("zcu102", "xczu9egffvb1156", "jtag-smt2-nc", 0, 0, CABLE_DEFAULT),
|
2022-05-16 08:41:35 +02:00
|
|
|
JTAG_BOARD("zcu106", "xczu7evffvc1156", "jtag-smt2-nc", 0, 0, CABLE_DEFAULT),
|
2023-03-09 20:48:19 +01:00
|
|
|
JTAG_BOARD("kcu116", "xcku5p-ffvb676", "jtag-smt2-nc", 0, 0, CABLE_DEFAULT),
|
2022-01-26 16:29:35 +01:00
|
|
|
JTAG_BOARD("zedboard", "xc7z020clg484", "digilent_hs2", 0, 0, CABLE_DEFAULT),
|
2023-02-09 21:49:03 +01:00
|
|
|
JTAG_BOARD("zybo_z7_10", "xc7z010clg400", "digilent", 0, 0, CABLE_DEFAULT),
|
|
|
|
|
JTAG_BOARD("zybo_z7_20", "xc7z020clg400", "digilent", 0, 0, CABLE_DEFAULT)
|
2019-09-26 18:29:20 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
#endif
|
