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openFPGALoader
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openFPGALoader/src/board.hpp

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move to APACHE-2.0 license
2021-06-26 15:24:07 +02:00
// SPDX-License-Identifier: Apache-2.0
/*
* Copyright (C) 2019 Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
*/
initial commit
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#ifndef BOARD_HPP
#define BOARD_HPP
#include <map>
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#include "cable.hpp"
/* AN_232R-01_Bit_Bang_Mode_Available_For_FT232R_and_Ft245R */
enum {
main,board,ftdiJtagBitbang: use pin ID instead of shift
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FT232RL_TXD = 0,
FT232RL_RXD = 1,
FT232RL_RTS = 2,
FT232RL_CTS = 3,
FT232RL_DTR = 4,
FT232RL_DSR = 5,
FT232RL_DCD = 6,
FT232RL_RI = 7
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};
/* AN_108_Command_Processor_for_MPSSE_and_MCU_Host_Bus_Emulation_Modes */
enum {
board: typo
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DBUS0 = (1 << 0),
DBUS1 = (1 << 1),
DBUS2 = (1 << 2),
DBUS3 = (1 << 3),
DBUS4 = (1 << 4),
DBUS5 = (1 << 5),
DBUS6 = (1 << 6),
DBUS7 = (1 << 7),
CBUS0 = (1 << 8),
CBUS1 = (1 << 9),
CBUS2 = (1 << 10),
CBUS3 = (1 << 11),
CBUS4 = (1 << 12),
CBUS5 = (1 << 13),
CBUS6 = (1 << 14),
CBUS7 = (1 << 15)
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};
/*!
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* \brief for bitbang mode this structure provide value for each JTAG signals
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*/
typedef struct {
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uint8_t tms_pin; /*! TMS pin value */
uint8_t tck_pin; /*! TCK pin value */
uint8_t tdi_pin; /*! TDI pin value */
uint8_t tdo_pin; /*! TDO pin value */
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} jtag_pins_conf_t;
board: add spi_pins_conf structure
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typedef struct {
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uint16_t cs_pin; /*! CS pin value */
uint16_t sck_pin; /*! SCK pin value */
uint16_t miso_pin; /*! MISO pin value */
uint16_t mosi_pin; /*! MOSI pin value */
uint16_t holdn_pin; /*! HOLDN pin value */
uint16_t wpn_pin; /*! WPN pin value */
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} spi_pins_conf_t;
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enum {
COMM_JTAG = (1 << 0),
add proof of concept / draft for DFU protocol. Add orangeCrab in DFU mode
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COMM_SPI = (1 << 1),
COMM_DFU = (1 << 2),
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};
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/*!
* \brief a board has a target cable and optionnally a pin configuration
* (bitbang mode)
*/
typedef struct {
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std::string manufacturer;
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std::string cable_name; /*! provide name of one entry in cable_list */
rework xilinx fpga spiOverJtag to respect model/package
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std::string fpga_part; /*! provide full fpga model name with package */
board: fix control pins size
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uint16_t reset_pin; /*! reset pin value */
uint16_t done_pin; /*! done pin value */
efinix: add jtag support, introduce oe_pin in board configuration, add xyloni jtag interface
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uint16_t oe_pin; /*! output enable pin value */
board: fix control pins size
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uint16_t mode; /*! communication type (JTAG or SPI) */
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jtag_pins_conf_t jtag_pins_config; /*! for bitbang, provide struct with pins value */
spi_pins_conf_t spi_pins_config; /*! for SPI, provide struct with pins value */
Allow board configuration table to contain a default clock speed (as some boards are known to work at higher speeds safely). Move Digilent Arty to 10MHz (tested).
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uint32_t default_freq; /* Default clock speed: 0 = use cable default */
board: add vid/pid for DFU at board level
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uint16_t vid; /* optional VID: used only with DFU */
uint16_t pid; /* optional VID: used only with DFU */
board: fix altsetting default for non-DFU boards, use signed type
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int16_t altsetting; /* optional altsetting: used only with DFU */
rework xilinx fpga spiOverJtag to respect model/package
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} target_board_t;
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Allow board configuration table to contain a default clock speed (as some boards are known to work at higher speeds safely). Move Digilent Arty to 10MHz (tested).
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#define CABLE_DEFAULT 0
#define CABLE_MHZ(_m) ((_m) * 1000000)
#define JTAG_BOARD(_name, _fpga_part, _cable, _rst, _done, _freq) \
efinix: add jtag support, introduce oe_pin in board configuration, add xyloni jtag interface
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{_name, {"", _cable, _fpga_part, _rst, _done, 0, COMM_JTAG, {}, {}, _freq, 0, 0, -1}}
board: add default frequency option for BITBANG and SPI boards
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#define JTAG_BITBANG_BOARD(_name, _fpga_part, _cable, _rst, _done, _tms, _tck, _tdi, _tdo, _freq) \
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{_name, {"", _cable, _fpga_part, _rst, _done, 0, COMM_JTAG, { _tms, _tck, _tdi, _tdo }, {}, \
board: fix altsetting default for non-DFU boards, use signed type
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_freq, 0, 0, -1}}
efinix: add jtag support, introduce oe_pin in board configuration, add xyloni jtag interface
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#define SPI_BOARD(_name, _manufacturer, _cable, _rst, _done, _oe, _cs, _sck, _si, _so, _holdn, _wpn, _freq) \
{_name, {_manufacturer, _cable, "", _rst, _done, _oe, COMM_SPI, {}, \
board: fix altsetting default for non-DFU boards, use signed type
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{_cs, _sck, _so, _si, _holdn, _wpn}, _freq, 0, 0, -1}}
dfu/main: add args to select altsetting and add filter to select corresponding interface
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#define DFU_BOARD(_name, _fpga_part, _cable, _vid, _pid, _alt) \
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{_name, {"", _cable, _fpga_part, 0, 0, 0, COMM_DFU, {}, {}, 0, _vid, _pid, _alt}}
board: simplify board definition using preprocessor macro
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rework xilinx fpga spiOverJtag to respect model/package
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static std::map <std::string, target_board_t> board_list = {
adding xilinx AC701 development kit
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JTAG_BOARD("ac701", "xc7a200t2fbg676c", "digilent", 0, 0, CABLE_DEFAULT),
Allow board configuration table to contain a default clock speed (as some boards are known to work at higher speeds safely). Move Digilent Arty to 10MHz (tested).
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JTAG_BOARD("acornCle215", "xc7a200tsbg484", "", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("alchitry_au", "xc7a35tftg256", "ft2232", 0, 0, CABLE_DEFAULT),
arty A7 100t support
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/* left for backward compatibility, use right name instead */
Allow board configuration table to contain a default clock speed (as some boards are known to work at higher speeds safely). Move Digilent Arty to 10MHz (tested).
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JTAG_BOARD("arty", "xc7a35tcsg324", "digilent", 0, 0, CABLE_MHZ(10)),
arty A7 100t support
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JTAG_BOARD("arty_a7_35t", "xc7a35tcsg324", "digilent", 0, 0, CABLE_MHZ(10)),
JTAG_BOARD("arty_a7_100t", "xc7a100tcsg324", "digilent", 0, 0, CABLE_MHZ(10)),
Digilent arty s7 25
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JTAG_BOARD("arty_s7_25", "xc7s25csga324", "digilent", 0, 0, CABLE_DEFAULT),
board: add arty S7 50
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JTAG_BOARD("arty_s7_50", "xc7s50csga324", "digilent", 0, 0, CABLE_DEFAULT),
digilent_arty_z7 10/20 support
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JTAG_BOARD("arty_z7_10", "xc7z010clg400", "digilent", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("arty_z7_20", "xc7z020clg400", "digilent", 0, 0, CABLE_DEFAULT),
board: alinx AXU2CGA
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JTAG_BOARD("axu2cga", "xczu2cg", "", 0, 0, CABLE_DEFAULT),
Allow board configuration table to contain a default clock speed (as some boards are known to work at higher speeds safely). Move Digilent Arty to 10MHz (tested).
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JTAG_BOARD("basys3", "xc7a35tcpg236", "digilent", 0, 0, CABLE_DEFAULT),
add support for CmodA7-35T digilent fpga board
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JTAG_BOARD("cmoda7_35t", "xc7a35tcpg236", "digilent", 0, 0, CABLE_DEFAULT),
Allow board configuration table to contain a default clock speed (as some boards are known to work at higher speeds safely). Move Digilent Arty to 10MHz (tested).
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JTAG_BOARD("nexysVideo", "xc7a200tsbg484", "digilent_b", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("kc705", "", "digilent", 0, 0, CABLE_DEFAULT),
no dash for zedboard fpga name
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JTAG_BOARD("zc702", "xc7z020clg484", "digilent", 0, 0, CABLE_DEFAULT),
Add digilent_zybo_z7 10/20 support
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JTAG_BOARD("zybo_z7_10", "xc7z010clg400", "digilent", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("zybo_z7_20", "xc7z020clg400", "digilent", 0, 0, CABLE_DEFAULT),
Allow board configuration table to contain a default clock speed (as some boards are known to work at higher speeds safely). Move Digilent Arty to 10MHz (tested).
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JTAG_BOARD("colorlight", "", "", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("colorlight-i5", "", "cmsisdap", 0, 0, CABLE_DEFAULT),
add support for colorlight-i9
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JTAG_BOARD("colorlight-i9", "", "cmsisdap", 0, 0, CABLE_DEFAULT),
Allow board configuration table to contain a default clock speed (as some boards are known to work at higher speeds safely). Move Digilent Arty to 10MHz (tested).
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JTAG_BOARD("crosslinknx_evn", "", "ft2232", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("cyc1000", "10cl025256", "ft2232", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("de0", "", "usb-blaster",0, 0, CABLE_DEFAULT),
JTAG_BOARD("de0nano", "ep4ce2217", "usb-blaster",0, 0, CABLE_DEFAULT),
JTAG_BOARD("de0nanoSoc", "", "usb-blasterII",0, 0, CABLE_DEFAULT),
JTAG_BOARD("de10nano", "", "usb-blasterII",0, 0, CABLE_DEFAULT),
board: add Terasic DE1-SoC board
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JTAG_BOARD("de1Soc", "5CSEMA5", "usb-blasterII",0, 0, CABLE_DEFAULT),
Allow board configuration table to contain a default clock speed (as some boards are known to work at higher speeds safely). Move Digilent Arty to 10MHz (tested).
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JTAG_BOARD("ecp5_evn", "", "ft2232", 0, 0, CABLE_DEFAULT),
rework xilinx fpga spiOverJtag to respect model/package
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SPI_BOARD("fireant", "efinix", "ft232",
efinix: add jtag support, introduce oe_pin in board configuration, add xyloni jtag interface
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DBUS4, DBUS5, 0, DBUS3, DBUS0, DBUS1, DBUS2, DBUS6, 0, CABLE_DEFAULT),
dfu/main: add args to select altsetting and add filter to select corresponding interface
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DFU_BOARD("fomu", "", "dfu", 0x1209, 0x5bf0, 0),
colognechip integration: initial commit This commit adds support for the Cologne Chip GateMate FPGA series. Both Evaluation Board and Programmer Cable are supported. Configurations can be loaded into the FPGA with both devices via JTAG or SPI. In addition to reading/writing data from/to flashes directly via SPI, this can also be done via the built-in JTAG-SPI-bypass. A direct wiring between programming hardware and flash is no longer necessary in this case. Signed-off-by: Patrick Urban <patrick.urban@web.de>
2021-12-10 12:12:32 +01:00
SPI_BOARD("gatemate_pgm_spi", "colognechip", "gatemate_pgm",
DBUS4, DBUS5, CBUS0, DBUS3, DBUS0, DBUS1, DBUS2, 0, 0, CABLE_DEFAULT),
JTAG_BOARD("gatemate_evb_jtag", "", "gatemate_evb_jtag", 0, 0, CABLE_DEFAULT),
SPI_BOARD("gatemate_evb_spi", "colognechip", "gatemate_evb_spi",
DBUS4, DBUS5, CBUS0, DBUS3, DBUS0, DBUS1, DBUS2, 0, 0, CABLE_DEFAULT),
add support for ice40 FPGA and iCEBreaker, icestick, iCE40-HX8K, iCE40-HX1K-EVN boards
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/* most ice40 boards uses the same pinout */
rework xilinx fpga spiOverJtag to respect model/package
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SPI_BOARD("ice40_generic", "lattice", "ft2232",
efinix: add jtag support, introduce oe_pin in board configuration, add xyloni jtag interface
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DBUS7, DBUS6, 0,
add support for ice40 FPGA and iCEBreaker, icestick, iCE40-HX8K, iCE40-HX1K-EVN boards
2020-10-31 15:02:54 +01:00
DBUS4, DBUS0, DBUS1, DBUS2,
board: add default frequency option for BITBANG and SPI boards
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0, 0, CABLE_DEFAULT),
board: generic FTDI SPI
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SPI_BOARD("ft2232_spi", "none", "ft2232",
DBUS7, DBUS6, 0,
DBUS4, DBUS0, DBUS1, DBUS2,
0, 0, CABLE_DEFAULT),
board: add support for 1bitsquared iCEBreaker-bitsy
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DFU_BOARD("icebreaker-bitsy", "", "dfu", 0x1d50, 0x6146, 0),
Allow board configuration table to contain a default clock speed (as some boards are known to work at higher speeds safely). Move Digilent Arty to 10MHz (tested).
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JTAG_BOARD("machXO2EVN", "", "ft2232", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("machXO3SK", "", "ft2232", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("machXO3EVN", "", "ft2232", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("licheeTang", "", "anlogicCable", 0, 0, CABLE_DEFAULT),
board: add entry for tec0117
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/* left for backward compatibility, use tec0117 instead */
Allow board configuration table to contain a default clock speed (as some boards are known to work at higher speeds safely). Move Digilent Arty to 10MHz (tested).
2021-07-11 16:20:15 +02:00
JTAG_BOARD("littleBee", "", "ft2232", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("spartanEdgeAccelBoard", "", "",0, 0, CABLE_DEFAULT),
JTAG_BOARD("pipistrello", "xc6slx45csg324", "ft2232", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("minispartan6", "", "ft2232", 0, 0, CABLE_DEFAULT),
dfu/main: add args to select altsetting and add filter to select corresponding interface
2021-10-03 12:39:06 +02:00
DFU_BOARD("orangeCrab", "", "dfu", 0x1209, 0x5af0, 0),
spiOverJtag: add bitstream for ECP4CE15F23
2021-11-28 16:50:13 +01:00
JTAG_BOARD("qmtechCycloneIV", "ep4ce1523", "", 0, 0, CABLE_DEFAULT),
Allow board configuration table to contain a default clock speed (as some boards are known to work at higher speeds safely). Move Digilent Arty to 10MHz (tested).
2021-07-11 16:20:15 +02:00
JTAG_BOARD("qmtechCycloneV", "5ce223", "", 0, 0, CABLE_DEFAULT),
Rename 5cefa5f23 to 5ce523, add documentation for board and fpga
2022-03-13 14:14:52 +01:00
JTAG_BOARD("qmtechCycloneV_5ce523", "5ce523", "", 0,0, CABLE_DEFAULT),
Remove the Tigard default cable, as the board does not have an on-board JTAG adapter.
2022-02-19 07:44:49 +01:00
JTAG_BOARD("qmtechKintex7", "xc7k325tffg676", "", 0, 0, CABLE_DEFAULT),
Update board.hpp Use default cable. This is equivalent to 6MHz setting, albeit more versatile.
2022-02-22 04:05:37 +01:00
JTAG_BOARD("genesys2", "xc7k325tffg900", "digilent_b", 0, 0, CABLE_DEFAULT),
board: PYNQ-Z2
2022-03-12 14:54:24 +01:00
JTAG_BOARD("pynq_z2", "xc7z020clg400", "ft2232", 0, 0, CABLE_DEFAULT),
board: add CERN SPEC150
2022-03-03 15:40:42 +01:00
JTAG_BOARD("spec150", "xc6slx150tfgg484", "", 0, 0, CABLE_DEFAULT),
Allow board configuration table to contain a default clock speed (as some boards are known to work at higher speeds safely). Move Digilent Arty to 10MHz (tested).
2021-07-11 16:20:15 +02:00
JTAG_BOARD("runber", "", "ft232", 0, 0, CABLE_DEFAULT),
ch552_jtag: driver for ch552_jtag firmware (ft2232c clone)
2021-11-06 10:33:25 +01:00
JTAG_BOARD("tangnano", "", "ch552_jtag", 0, 0, CABLE_DEFAULT),
board: add tangnano1k to board_list
2022-01-28 12:53:33 +01:00
JTAG_BOARD("tangnano1k", "", "ft2232", 0, 0, CABLE_DEFAULT),
adding reference to Tang Nano 4K kit in doc
2021-09-02 13:54:34 +02:00
JTAG_BOARD("tangnano4k", "", "ft2232", 0, 0, CABLE_DEFAULT),
tangnano9k: new board, with the same cable w/ tangnano4k Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2022-01-22 13:51:05 +01:00
JTAG_BOARD("tangnano9k", "", "ft2232", 0, 0, CABLE_DEFAULT),
board: adding sipeed Tang Primer 20k
2022-07-26 20:25:02 +02:00
JTAG_BOARD("tangprimer20k", "", "ft2232", 0, 0, CABLE_DEFAULT),
Allow board configuration table to contain a default clock speed (as some boards are known to work at higher speeds safely). Move Digilent Arty to 10MHz (tested).
2021-07-11 16:20:15 +02:00
JTAG_BOARD("tec0117", "", "ft2232", 0, 0, CABLE_DEFAULT),
ORBTrace Mini support (DFU mode)
2022-06-18 22:55:58 +02:00
DFU_BOARD("orbtrace_dfu", "", "dfu", 0x1209, 0x3442, 1),
board: add default frequency option for BITBANG and SPI boards
2021-07-14 08:05:36 +02:00
JTAG_BITBANG_BOARD("ulx2s", "", "ft232RL", 0, 0,
FT232RL_RI, FT232RL_DSR, FT232RL_CTS, FT232RL_DCD, CABLE_DEFAULT),
JTAG_BITBANG_BOARD("ulx3s", "", "ft231X", 0, 0,
FT232RL_DCD, FT232RL_DSR, FT232RL_RI, FT232RL_CTS, CABLE_DEFAULT),
board: ulx3s_dfu
2021-12-24 18:10:22 +01:00
DFU_BOARD("ulx3s_dfu", "", "dfu", 0x1d50, 0x614b, 0),
Allow board configuration table to contain a default clock speed (as some boards are known to work at higher speeds safely). Move Digilent Arty to 10MHz (tested).
2021-07-11 16:20:15 +02:00
JTAG_BOARD("ecpix5", "", "ecpix5-debug", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("xtrx", "xc7a50tcpg236", "" , 0, 0, CABLE_DEFAULT),
efinix: add jtag support, introduce oe_pin in board configuration, add xyloni jtag interface
2021-10-23 08:44:23 +02:00
JTAG_BOARD("xyloni_jtag", "", "efinix_jtag_ft4232" , 0, 0, CABLE_DEFAULT),
Add Trion T120 BGA 576 Dev Kit support. This Dev Kit uses a FT2232 chip, so also rename efinix_spi with efinix_spi_ft4232 and introduce efinix_spi_ft2232.
2021-10-15 09:17:59 +02:00
SPI_BOARD("xyloni_spi", "efinix", "efinix_spi_ft4232",
efinix: add jtag support, introduce oe_pin in board configuration, add xyloni jtag interface
2021-10-23 08:44:23 +02:00
DBUS4, DBUS5, DBUS7, DBUS3, DBUS0, DBUS1, DBUS2, DBUS6, 0, CABLE_DEFAULT),
Add Trion T120 BGA 576 Dev Kit support. This Dev Kit uses a FT2232 chip, so also rename efinix_spi with efinix_spi_ft4232 and introduce efinix_spi_ft2232.
2021-10-15 09:17:59 +02:00
SPI_BOARD("trion_t120_bga576","efinix", "efinix_spi_ft2232",
efinix: add jtag support, introduce oe_pin in board configuration, add xyloni jtag interface
2021-10-23 08:44:23 +02:00
DBUS4, DBUS5, DBUS7, DBUS3, DBUS0, DBUS1, DBUS2, DBUS6, 0, CABLE_DEFAULT),
JTAG_BOARD("trion_t120_bga576_jtag", "", "ft2232_b", 0, 0, CABLE_DEFAULT),
efinix: add support for Titanium Ti60 f225 dev kit
2021-12-13 22:13:29 +01:00
SPI_BOARD("titanium_ti60_f225","efinix", "efinix_spi_ft4232",
DBUS4, DBUS5, DBUS7, DBUS3, DBUS0, DBUS1, DBUS2, DBUS6, 0, CABLE_DEFAULT),
JTAG_BOARD("titanium_ti60_f225_jtag", "","efinix_jtag_ft4232", 0, 0, CABLE_DEFAULT),
board: Xilinx ZC706
2022-03-10 18:53:41 +01:00
JTAG_BOARD("zc706", "xc7z045ffg900", "jtag-smt2-nc", 0, 0, CABLE_DEFAULT),
board: Xilinx ZCU102
2022-03-19 10:08:51 +01:00
JTAG_BOARD("zcu102", "xczu9egffvb1156", "jtag-smt2-nc", 0, 0, CABLE_DEFAULT),
Correct part number for ZCU106 board
2022-05-16 08:41:35 +02:00
JTAG_BOARD("zcu106", "xczu7evffvc1156", "jtag-smt2-nc", 0, 0, CABLE_DEFAULT),
no dash for zedboard fpga name
2022-01-26 16:29:35 +01:00
JTAG_BOARD("zedboard", "xc7z020clg484", "digilent_hs2", 0, 0, CABLE_DEFAULT),
Support for the Papilio One board
2022-03-25 21:44:05 +01:00
JTAG_BOARD("papilio_one", "xc3s500evq100", "papilio", 0, 0, CABLE_DEFAULT),
initial commit
2019-09-26 18:29:20 +02:00
};
#endif