openFPGALoader/src/board.hpp

71 lines
2.0 KiB
C++
Raw Normal View History

2019-09-26 18:29:20 +02:00
#ifndef BOARD_HPP
#define BOARD_HPP
#include <map>
#include "cable.hpp"
/* AN_232R-01_Bit_Bang_Mode_Available_For_FT232R_and_Ft245R */
enum {
FT232RL_TXD = 0,
FT232RL_RXD = 1,
FT232RL_RTS = 2,
FT232RL_CTS = 3,
FT232RL_DTR = 4,
FT232RL_DSR = 5,
FT232RL_DCD = 6,
FT232RL_RI = 7
};
/*!
* \brief for bitbang mode this structure provide offset for each JTAG signals
*/
typedef struct {
uint8_t tms_pin; /*! TMS pin offset */
uint8_t tck_pin; /*! TCK pin offset */
uint8_t tdi_pin; /*! TDI pin offset */
uint8_t tdo_pin; /*! TDO pin offset */
} jtag_pins_conf_t;
2020-10-30 08:23:49 +01:00
typedef struct {
uint8_t cs_pin; /*! CS pin offset */
uint8_t sck_pin; /*! SCK pin offset */
uint8_t miso_pin; /*! MISO pin offset */
uint8_t mosi_pin; /*! MOSI pin offset */
uint8_t holdn_pin; /*! HOLDN pin offset */
uint8_t wpn_pin; /*! WPN pin offset */
} spi_pins_conf_t;
/*!
* \brief a board has a target cable and optionnally a pin configuration
* (bitbang mode)
*/
typedef struct {
std::string cable_name; /*! provide name of one entry in cable_list */
jtag_pins_conf_t pins_config; /*! for bitbang, provide struct with pins offset */
} target_cable_t;
static std::map <std::string, target_cable_t> board_list = {
{"arty", {"digilent", {}}},
{"nexysVideo", {"digilent_b", {}}},
{"colorlight", {"", {}}},
2020-09-26 08:47:26 +02:00
{"crosslinknx_evn", {"ft2232", {}}},
{"cyc1000", {"ft2232", {}}},
{"de0nano", {"usb-blaster",{}}},
{"ecp5_evn", {"ft2232", {}}},
{"machXO2EVN", {"ft2232", {}}},
{"machXO3SK", {"ft2232", {}}},
2020-10-16 08:03:45 +02:00
{"machXO3EVN", {"ft2232", {}}},
{"licheeTang", {"anlogicCable", {}}},
{"littleBee", {"ft2232", {}}},
{"spartanEdgeAccelBoard", {"",{}}},
2020-04-28 18:22:33 +02:00
{"pipistrello", {"ft2232", {}}},
{"qmtechCycloneV", {"", {}}},
2020-03-07 11:53:13 +01:00
{"tangnano", {"ft2232", {}}},
2020-03-07 18:46:41 +01:00
{"ulx2s", {"ft232RL", {FT232RL_RI, FT232RL_DSR, FT232RL_CTS, FT232RL_DCD}}},
2020-05-12 19:09:30 +02:00
{"ulx3s", {"ft231X", {FT232RL_DCD, FT232RL_DSR, FT232RL_RI, FT232RL_CTS}}},
{"ecpix5", {"ecpix5-debug", {}}},
2019-09-26 18:29:20 +02:00
};
#endif