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5208 Commits

Author SHA1 Message Date
gatecat 6927dbe548 fixup! gatemate: Override router2 cost function to account for low-delay pips 2026-08-15 11:21:53 +02:00
gatecat 6710ec45aa wip: cost of existing routing on heap 2026-08-15 11:01:41 +02:00
gatecat 9b117b8b95 wip midpoint revisit 2026-08-14 17:10:00 +02:00
gatecat 3d71bf678c gatemate: Override router2 cost function to account for low-delay pips 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-08-14 16:48:48 +02:00
gatecat 4d23515026 router2: Fix reservation around pre-routed nets 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-08-13 15:09:45 +02:00
gatecat 3e8ddf3a77 gatemate: Reserve one level further uphill if needed 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-08-13 14:38:52 +02:00
gatecat c6eca2405b gatemate: Also use clock router for RAM clocks 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-08-13 13:33:33 +02:00
gatecat 51e703d094 static: Enable dark node insertion only for non-logic 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-08-12 10:36:06 +02:00
gatecat 930fef448e static: Allow a custom delay prediction function 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-08-11 15:57:13 +02:00
gatecat df871def22 xilinx: Small tweak to delay prediction 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-08-11 15:03:04 +02:00
gatecat a435792828 nexus: Disconnect CCU2 CIN when it's a don't care 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-08-11 13:43:31 +02:00
bin 62e659ed67 Fix compilation with `NPNR_DISABLE_THREADS`. 2026-08-10 01:09:59 +01:00
Jasper Homann c73affb3dc Only delete old context after emitting context changed wiht new context when inporting json 2026-08-07 15:19:25 +02:00
Jasper Homann 9a4652e0f8 Protect json import with mutex 
Signed-off-by: Jasper Homann <jasper.homann@tu-braunschweig.de>
 2026-08-07 15:19:25 +02:00
Jasper Homann d3bbf4dc6e gui: Properly initialize himbaechel context when creating a new one during json import 
Signed-off-by: Jasper Homann <jasper.homann@tu-braunschweig.de>
 2026-08-07 15:19:25 +02:00
Catherine de8cd9782f Accept UTF-8 filenames and terminal I/O on Windows. 2026-08-06 17:49:16 +02:00
Jasper Homann 8f6cab0fc8
gatemate: Place CC_MULT packed P register in same row (#1771) 
Signed-off-by: Jasper Homann <jasper.homann@tu-braunschweig.de>
 2026-08-05 23:49:49 +01:00
gatecat 8d8053e0c5 xilinx: Make router2 default 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-08-04 14:52:44 +02:00
gatecat a3938de734 clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-08-04 10:51:28 +02:00
gatecat d324239345 xilinx: clean up some compiler warnings 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-08-04 10:51:04 +02:00
gatecat 049f38659a util: Replace use of strcasecmp in boolstr_or_default 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-08-04 10:47:56 +02:00
gatecat 44a4d1e6cd xilinx: don't use 'or' operator 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-08-04 10:46:00 +02:00
gatecat 0d4fffae10 Fix BaseArch::archId() 
Fixes #1761

Signed-off-by: gatecat <gatecat@ds0.me>
 2026-08-04 10:41:12 +02:00
YRabbit 2fb1d1982f Gowin. Fix wire IDs leak. 
In some cases, wires with the same name were being re-created.

This affected both the creation of shared primitive ports and changing
the wire type if the cell had an additional function.

Here, we separate wire creation and type change into a separate function and use it in most cases.

Addresses: https://github.com/YosysHQ/nextpnr/issues/1759

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2026-08-03 15:51:32 +02:00
Lunaphied 8945407874 docs/viaduct: don't reference nonexistent architecture in documentation 2026-08-02 20:02:31 +02:00
gatecat 90b9be4859 router2: Fix ripup of constant nets 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-08-01 15:43:10 +02:00
Jonas K. 68c1acd80a fabulous: move timing-arc helpers to bel_timing.cc 
Extract TimingPredicate/BelTimingArc and the parse/eval/apply timing
helpers out of fabulous.cc into bel_timing.cc/h.
 2026-07-29 15:20:52 +02:00
Jonas K. ef6931f440 fabulous: add generic way to set BEL timings and placer/router tunables 
Add bel.v3.txt, which carries per-arc BEL timing (Delay/SetupHold/
ClkToOut/Clock) with config-bit conditions, on top of bel.v2's structural
blocks. Timing is applied per instance: a representative per-type estimate in
prePlace, then each placed BEL's own arcs in postPlace (bel_timing_by_bel,
keyed by BelId).

Add placement_estimate.txt carrying BEL timing estimates and nextpnr
placer/router tunables (delayScale/delayOffset/delayEpsilon/ripupPenalty/
carryPredictDelay, each defaulting to nextpnr's historical hardcoded value).

A more detailed description of the FABulous model files can be found here:
https://fabulous.readthedocs.io/en/latest/user_guide/using_doc/pnr/nextpnr.html#bel-v3-txt-bel-timing

bel.v3.txt and placement_estimate.txt were added as separate files
to keep compatibility with older nextpnr versions and existing fabulous projects.

A few cosmetics and comments added.
 2026-07-29 15:20:52 +02:00
Lunaphied 00376b6b0d qt: remove qt5 as it's no longer relevant and clean up some warnings 2026-07-28 19:09:50 +02:00
Miodrag Milanovic 77e1f19f21 gatemate: fixed test assert 2026-07-27 14:52:21 +02:00
gatecat bf63271fe7 ice40: Allow disablement of CE global promotion 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-07-27 11:32:18 +02:00
gatecat a6a6afa827 ice40: Add noglobal attribute and raise promotion threshold 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-07-27 11:32:18 +02:00
gitRaiku 498f0422cd himbaechel: Merge all test entrypoints into one 
This commit merges every main() for every uarch into asingle one.
This fixes a build error when building tests for every uarch at once.

Signed-off-by: gitRaiku <raraiku@proton.me>
 2026-07-27 11:01:32 +02:00
gatecat bf80306e97 nexus: Fix OSHX primitives 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-07-27 10:52:12 +02:00
Jasper Homann fb95bb8ea1
gatemate: Fix DFF pin names when packing mult p registers (#1755) 2026-07-24 14:06:38 +01:00
gatecat a7b62d7cb8 nexus: Fix memory corruption due to rehash 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-07-24 13:52:18 +02:00
gatecat da46844ca6 nexus: Fix slow routing around DQSBUFs 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-07-22 14:03:42 +02:00
gatecat f8097c3127 nexus: Initial improvements to edge clock routing 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-07-22 13:55:15 +02:00
gatecat c2cbdc7efa nexus: Initial support for DDR3 memory interfaces 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-07-21 17:58:52 +02:00
gatecat ddc6c8c8b9 nexus: Place ECLK bels 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-07-19 10:46:49 +02:00
gatecat 5eddc52881 nexus: Add other IODDR modes 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-07-18 14:11:24 +02:00
gatecat 02d57cfaa1 nexus: Add mapping for IDDRX2 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-07-18 13:50:27 +02:00
gatecat 452e75bad6 nexus: Add a mapping for ODDRX2 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-07-18 13:35:13 +02:00
gatecat ab65039755 nexus: Add ECLK bels 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-07-18 13:09:37 +02:00
gatecat 60ee033cca ci: Bump prjoxide version 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-07-18 12:24:36 +02:00
gatecat 1831ce9510 nexus: Add DQS routing to BBA 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-07-18 11:45:24 +02:00
gatecat 7c667eeba3 ecp5: Prioritise ECLK usage when placing PLLs 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-07-17 12:27:24 +02:00
gatecat 8624a48bcf ecp5: Make fabric routed ECLK an error 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-07-17 12:27:24 +02:00
gatecat 261152be8a ecp5: IDDRX2F has ALIGNWD too 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-07-14 14:53:17 +02:00
Lofty 4c72cee9ee
gatemate, ng-ultra: add micko and I as code owners (#1747) 2026-07-12 12:43:35 +02:00