mirror of https://github.com/YosysHQ/nextpnr.git
nexus: Add other IODDR modes
Signed-off-by: gatecat <gatecat@ds0.me>
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02d57cfaa1
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5eddc52881
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@ -1303,30 +1303,30 @@ struct NexusPacker
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iol_rules[id_ODDRX1].port_xform[id_D0] = id_TXDATA0;
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iol_rules[id_ODDRX1].port_xform[id_D1] = id_TXDATA1;
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iol_rules[id_ODDRX2].new_type = id_IOLOGIC;
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iol_rules[id_ODDRX2].set_params.emplace_back(id_MODE, std::string("ODDRXN"));
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iol_rules[id_ODDRX2].set_params.emplace_back(ctx->id("ODDRXN.DDRMODE"), std::string("ODDRX2"));
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iol_rules[id_ODDRX2].port_xform[id_ECLK] = id_ECLK;
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iol_rules[id_ODDRX2].port_xform[id_SCLK] = id_SCLKOUT;
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iol_rules[id_ODDRX2].port_xform[id_RST] = id_LSROUT;
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iol_rules[id_ODDRX2].port_xform[id_Q] = id_DOUT;
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iol_rules[id_ODDRX2].port_xform[id_D0] = id_TXDATA0;
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iol_rules[id_ODDRX2].port_xform[id_D1] = id_TXDATA1;
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iol_rules[id_ODDRX2].port_xform[id_D2] = id_TXDATA2;
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iol_rules[id_ODDRX2].port_xform[id_D3] = id_TXDATA3;
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for (int gear : {2, 4, 5}) {
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IdString otype = ctx->idf("ODDRX%d", gear);
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iol_rules[otype].new_type = id_IOLOGIC;
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iol_rules[otype].set_params.emplace_back(id_MODE, std::string("ODDRXN"));
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iol_rules[otype].set_params.emplace_back(ctx->id("ODDRXN.DDRMODE"), otype.str(ctx));
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iol_rules[otype].port_xform[id_ECLK] = id_ECLK;
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iol_rules[otype].port_xform[id_SCLK] = id_SCLKOUT;
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iol_rules[otype].port_xform[id_RST] = id_LSROUT;
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iol_rules[otype].port_xform[id_Q] = id_DOUT;
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for (int i = 0; i < 2 * gear; i++)
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iol_rules[otype].port_xform[ctx->idf("D%d", i)] = ctx->idf("TXDATA%d", i);
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iol_rules[id_IDDRX2].new_type = id_IOLOGIC;
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iol_rules[id_IDDRX2].set_params.emplace_back(id_MODE, std::string("IDDRXN"));
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iol_rules[id_IDDRX2].set_params.emplace_back(ctx->id("IDDRXN.DDRMODE"), std::string("IDDRX2"));
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iol_rules[id_IDDRX2].port_xform[id_ECLK] = id_ECLK;
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iol_rules[id_IDDRX2].port_xform[id_SCLK] = id_SCLKIN;
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iol_rules[id_IDDRX2].port_xform[id_RST] = id_LSRIN;
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iol_rules[id_IDDRX2].port_xform[id_ALIGNWD] = id_WORDALIGN;
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iol_rules[id_IDDRX2].port_xform[id_D] = id_DI;
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iol_rules[id_IDDRX2].port_xform[id_Q0] = id_RXDATA6;
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iol_rules[id_IDDRX2].port_xform[id_Q1] = id_RXDATA7;
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iol_rules[id_IDDRX2].port_xform[id_Q2] = id_RXDATA8;
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iol_rules[id_IDDRX2].port_xform[id_Q3] = id_RXDATA9;
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IdString itype = ctx->idf("IDDRX%d", gear);
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iol_rules[itype].new_type = id_IOLOGIC;
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iol_rules[itype].set_params.emplace_back(id_MODE, std::string("IDDRXN"));
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iol_rules[itype].set_params.emplace_back(ctx->id("IDDRXN.DDRMODE"), itype.str(ctx));
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iol_rules[itype].port_xform[id_ECLK] = id_ECLK;
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iol_rules[itype].port_xform[id_SCLK] = id_SCLKIN;
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iol_rules[itype].port_xform[id_RST] = id_LSRIN;
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iol_rules[itype].port_xform[id_ALIGNWD] = id_WORDALIGN;
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iol_rules[itype].port_xform[id_D] = id_DI;
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for (int i = 0; i < 2 * gear; i++)
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iol_rules[itype].port_xform[ctx->idf("Q%d", i)] = ctx->idf("RXDATA%d", (10 - 2 * gear) + i);
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}
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generic_xform(iol_rules, true);
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}
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@ -230,15 +230,23 @@ static const dict<IdString, Arch::CellPinsData> base_cell_pin_data = {
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}},
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{id_IOLOGIC,
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{{id_SCLKIN, PINSTYLE_IOL_CLK}, {id_SCLKOUT, PINSTYLE_IOL_CLK}, {id_LSRIN, PINSTYLE_IOL_CELSR},
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{id_LSROUT, PINSTYLE_IOL_CELSR}, {id_CEIN, PINSTYLE_IOL_CELSR}, {id_CEOUT, PINSTYLE_IOL_CELSR},
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{id_TXDATA0, PINSTYLE_CIB}, {id_TXDATA1, PINSTYLE_CIB}, {id_TXDATA2, PINSTYLE_CIB},
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{id_TXDATA3, PINSTYLE_CIB}, {id_TXDATA4, PINSTYLE_CIB}, {id_TXDATA5, PINSTYLE_CIB},
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{id_TXDATA6, PINSTYLE_CIB}, {id_TXDATA7, PINSTYLE_CIB}, {id_TXDATA8, PINSTYLE_CIB},
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{{id_SCLKIN, PINSTYLE_IOL_CLK},
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{id_SCLKOUT, PINSTYLE_IOL_CLK},
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{id_LSRIN, PINSTYLE_IOL_CELSR},
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{id_LSROUT, PINSTYLE_IOL_CELSR},
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{id_CEIN, PINSTYLE_IOL_CELSR},
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{id_CEOUT, PINSTYLE_IOL_CELSR},
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{id_TXDATA0, PINSTYLE_CIB},
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{id_TXDATA1, PINSTYLE_CIB},
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{id_TXDATA2, PINSTYLE_CIB},
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{id_TXDATA3, PINSTYLE_CIB},
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{id_TXDATA4, PINSTYLE_CIB},
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{id_TXDATA5, PINSTYLE_CIB},
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{id_TXDATA6, PINSTYLE_CIB},
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{id_TXDATA7, PINSTYLE_CIB},
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{id_TXDATA8, PINSTYLE_CIB},
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{id_TXDATA9, PINSTYLE_CIB},
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{id_TSDATA0, PINSTYLE_CIB}, {id_TSDATA1, PINSTYLE_CIB}, {id_TSDATA2, PINSTYLE_CIB},
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{id_TSDATA3, PINSTYLE_CIB}, {id_WORDALIGN, PINSTYLE_CIB}
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{id_WORDALIGN, PINSTYLE_CIB}
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}},
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{id_CONFIG_MULTIBOOT_CORE,
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