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xilinx: don't use 'or' operator 

Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2026-08-04 10:46:00 +02:00
parent 0d4fffae10
commit 44a4d1e6cd
1 changed files with 2 additions and 2 deletions
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4
himbaechel/uarch/xilinx/fasm.cc
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@ -1724,7 +1724,7 @@ struct FasmBackend
// but in real life, Vivado sets AREG_0 is 0,
// no bit is 1, and AREG_2 is 2
auto areg = int_or_default(ci->params, ctx->id("AREG"), 1);
if (areg == 0 or areg == 2)
if (areg == 0 || areg == 2)
write_bit("AREG_" + std::to_string(areg));
auto ainput = str_or_default(ci->params, ctx->id("A_INPUT"), "DIRECT");
@ -1735,7 +1735,7 @@ struct FasmBackend
// but in real life, Vivado sets AREG_0 is 0,
// no bit is 1, and AREG_2 is 2
auto breg = int_or_default(ci->params, ctx->id("BREG"), 1);
if (breg == 0 or breg == 2)
if (breg == 0 || breg == 2)
write_bit("BREG_" + std::to_string(breg));
auto binput = str_or_default(ci->params, ctx->id("B_INPUT"), "DIRECT");