nexus: Add ECLK bels

Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2026-07-18 13:09:37 +02:00
parent 60ee033cca
commit ab65039755
4 changed files with 35 additions and 3 deletions

View File

@ -525,6 +525,15 @@ X(SCLKOUT)
X(ECLK)
X(CEIN)
X(ECLKDIV)
X(ECLKDIV_CORE)
X(ECLKSYNC)
X(ECLKSYNC_CORE)
X(ECLKIN)
X(DIVOUT)
X(ECLKOUT)
X(IDDRX1)
X(ODDRX1)
X(TXDATA0)

View File

@ -577,6 +577,15 @@ struct NexusFasmWriter
write_enum(cell, "DCSMODE", "VCC");
pop(2);
}
// Write config for ECLKDIV
void write_eclkdiv(const CellInfo *cell)
{
BelId bel = cell->bel;
push_bel(bel);
write_enum(cell, "ECLK_DIV", "DISABLE");
write_enum(cell, "GSR", "DISABLED");
pop();
}
// Write config for an OXIDE_EBR cell
void write_bram(const CellInfo *cell)
{
@ -1142,6 +1151,8 @@ struct NexusFasmWriter
write_lmmi(ci);
else if (ci->type == id_CONFIG_CLKRST_CORE)
write_cfg_clkrst(ci);
else if (ci->type == id_ECLKDIV_CORE)
write_eclkdiv(ci);
blank();
}
// Handle DCC route-throughs

View File

@ -906,8 +906,9 @@ struct NexusPacker
for (size_t i = 0; i < std::min<size_t>(clk_fanout.size(), available_globals); i++) {
NetInfo *net = ctx->nets.at(clk_fanout.at(i).second).get();
log_info(" promoting clock net '%s'\n", ctx->nameOf(net));
insert_buffer(net, id_DCC, "glb_clk", id_CLKI, id_CLKO,
[&](const PortRef &port) { return port.cell->type != id_DCC; });
insert_buffer(net, id_DCC, "glb_clk", id_CLKI, id_CLKO, [&](const PortRef &port) {
return port.cell->type != id_DCC && !port.port.in(id_ECLK, id_ECLKIN);
});
}
}

View File

@ -257,7 +257,18 @@ static const dict<IdString, Arch::CellPinsData> base_cell_pin_data = {
{
{{}, PINSTYLE_DEDI},
}},
{id_ECLKDIV_CORE,
{
{{id_ECLKIN}, PINSTYLE_DEDI},
{{id_DIVOUT}, PINSTYLE_DEDI},
{{}, PINSTYLE_CIB},
}},
{id_ECLKSYNC_CORE,
{
{{id_ECLKIN}, PINSTYLE_DEDI},
{{id_ECLKOUT}, PINSTYLE_DEDI},
{{}, PINSTYLE_CIB},
}},
};
} // namespace