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nextpnr-0.1

nextpnr-0.10

nextpnr-0.11

nextpnr-0.11.1

nextpnr-0.2

nextpnr-0.3

nextpnr-0.4

nextpnr-0.5

nextpnr-0.6

nextpnr-0.7

nextpnr-0.8

nextpnr-0.9

Mono Color

• 8cd90d8b6f ecp5: Fix loading a pre-placed json main gatecat 2026-10-06 08:45:45 +02:00
• aa8c83b856 gatemate: Only bridge clocks through CPEs that are completely free (#1832) Patrick Urban 2026-10-05 16:23:26 +02:00
• 1e6050d50b ice40: Add support for SB_FILTER_50NS gatecat 2026-10-05 14:48:45 +02:00
• 6f71bc280b router2: skip RESERVED_UNAVAILABLE wires when reserving sink paths Robb WaltersandClaude Opus 5.5 2026-10-02 22:49:15 -07:00
• e2fe86b3ce Gowin. GW5AT-60B clocks. YRabbit 2026-10-02 11:30:03 +10:00
• f745549624 xilinx: require a shared WE net per SLICEM in logic tile validity Joris van Zwieten 2026-08-19 15:16:04 +02:00
• 899e82b3fa xilinx: error on unknown X_ORIG_PORT tokens in LUT init export Joris van Zwieten 2026-08-17 15:13:02 +02:00
• 826854d5c2 xilinx: fix separator when merging X_ORIG_PORT entries in fixup_routing Joris van Zwieten 2026-08-17 15:13:02 +02:00
• 9ddcaca3b6 himbaechel/xilinx: don't pair FFs with SRL/LUTRAM on a different clock Joris van ZwietenandClaude Fable 5 2026-07-30 15:44:01 +02:00
• 0c71b06aa3 himbaechel/xilinx: fix MMCM loop filter programming Joris van ZwietenandClaude Fable 5 2026-07-30 15:38:22 +02:00
• 408022fe22 heap: Use a vector for cell_locs gatecat 2026-09-21 17:22:11 +02:00
• eb4f15c35f gatemate: PLL's REF_CLK parameter has no upper limit (#1818) Patrick Urban 2026-09-29 15:02:23 +02:00
• ad8527f8f4 gatemate: only set IOBUF delays where connection exists Miodrag Milanovic 2026-09-29 08:50:36 +02:00
• c619da3de0 Himbaechel/xilinx : Report number of extra LUTs created during packing Adrien Prost-Boucle 2026-09-28 21:31:46 +02:00
• c7a4d81496 Himbaechel/xilinx : Better align indented reports Adrien Prost-Boucle 2026-09-25 22:49:52 +02:00
• 3c42800da0 gatemate: add missing timing check from and to IOSEL (#1814) Patrick Urban 2026-09-28 13:42:58 +02:00
• 073bb87efb clangformat gatecat 2026-09-28 13:22:17 +02:00
• c4fbb55a66 gowin: handle singleton vector [0] in CST constraints Carlos Venegas ArrabéandShriyans S Sahoo 2026-09-25 23:09:28 +02:00
• 1aea87ab50 gatemate: fix clock inversion for FF_OBF/FF_IBF pack Miodrag Milanovic 2026-09-25 08:57:01 +02:00
• 24781ef48e xilinx: Fix packing of RAM64X1S gatecat 2026-09-24 11:37:12 +02:00
• 3edea68ef3 Tidy up pin constraint handling for singleton vectors gatecat 2026-09-18 18:39:55 +02:00
• 3e53a0bf44 Merge pull request #1801 from FelipeCalliari/fix-related-clock-delay-sign Lofty 2026-09-17 11:19:21 +01:00
• 813d876d02 Fix build on GNU Hurd Simon Richter 2026-09-16 22:28:59 +09:00
• 6030081a15 gowin: fix carry-in adapter table for CIN from logic Hugo Sereno Ferreira 2026-09-13 03:10:25 +01:00
• f5164be536 timing: Fix sign of related clock-to-clock delay Felipe Calliari 2026-09-13 01:50:15 -03:00
• a601751d08 Remove long-unimplemented function and associated dead code gatecat 2026-09-10 10:38:03 +02:00
• e47c2589e8 himbaechel: Add support for GW_JTAG on TangNano20k / GW2A-18C (under instruction from YRabbit) Alastair M. Robinson 2026-09-08 19:03:50 +01:00
• 26438a556b Himbaechel Xilinx: Print one more decimal for PLL frequencies, for consistency and for better detailed report Adrien Prost-Boucle 2026-09-08 22:38:37 +02:00
• 591374c401 Himbaechel Xilinx: Fix inaccuracy at print of VCO frequency, caused by implicit cast from double to int Adrien Prost-Boucle 2026-09-08 22:33:29 +02:00
• 3cfc28d02e machxo2: Harmonise install instructions with other arches gatecat 2026-09-06 14:02:16 +02:00
• 6b58ca1376 router2: Fix handling of unavailable wires when reserving drivers gatecat 2026-09-06 13:55:49 +02:00
• 07b473030e fix stable sort distance calculation typo YH Law 2026-08-20 22:57:54 +08:00
• 8dbcee5c3c static: Improve log output gatecat 2026-08-31 15:29:51 +02:00
• dec04b3b64 router2: Replace the router1 call with ctx->checkRoutedDesign gatecat 2026-08-27 13:40:33 +02:00
• 68d0d07af5 himbaechel: Fix logic in updating pip delay structures gatecat 2026-08-27 09:45:42 +02:00
• 6087c564a0 Gowin. Disable optimization for custom ALU. YRabbit 2026-08-27 07:51:30 +10:00
• 914e84257d router2: Reduce redundancy in PerWireData gatecat 2026-08-26 10:46:22 +02:00
• 7d4f72c0aa clangformat gatecat 2026-08-26 09:45:26 +02:00
• bc1aec33d7 fabulous: Warn about bel.v3 clock pins with no arrival time Jonas K. 2026-08-21 19:21:56 +02:00
• 498e7c271a fabulous: Make the pips file delay scale settable Jonas K. 2026-08-21 19:12:31 +02:00
• 362bc76eea fabulous: Read the per-flop clock arrival time from bel.v3 Jonas K. 2026-08-21 19:10:45 +02:00
• 71b0d36fb1 fabulous: Drop support for the 1.0 project format Jonas K. 2026-08-21 19:09:32 +02:00
• b17408e290 Gowin. Add GW5AT-60B chip. YRabbit 2026-08-23 17:21:35 +10:00
• 7c0c1c4019 python: bind getWireDelay gatecat 2026-08-20 16:33:50 +02:00
• 6927dbe548 fixup! gatemate: Override router2 cost function to account for low-delay pips gatecat/r2-hacking gatecat 2026-08-15 11:15:13 +02:00
• 6710ec45aa wip: cost of existing routing on heap gatecat 2026-08-15 11:01:41 +02:00
• 9b117b8b95 wip midpoint revisit gatecat 2026-08-14 17:10:00 +02:00
• 3d71bf678c gatemate: Override router2 cost function to account for low-delay pips gatecat 2026-08-14 16:48:48 +02:00
• 4d23515026 router2: Fix reservation around pre-routed nets gatecat 2026-08-13 13:57:57 +02:00
• 3e8ddf3a77 gatemate: Reserve one level further uphill if needed gatecat 2026-08-13 09:57:25 +02:00
• c6eca2405b gatemate: Also use clock router for RAM clocks gatecat 2026-08-12 11:20:17 +02:00
• 51e703d094 static: Enable dark node insertion only for non-logic gatecat 2026-08-12 10:36:06 +02:00
• 930fef448e static: Allow a custom delay prediction function gatecat 2026-08-11 15:39:09 +02:00
• df871def22 xilinx: Small tweak to delay prediction gatecat 2026-08-11 15:03:04 +02:00
• a435792828 nexus: Disconnect CCU2 CIN when it's a don't care gatecat 2026-08-11 13:43:31 +02:00
• 62e659ed67 Fix compilation with NPNR_DISABLE_THREADS. nextpnr-0.11.1 bin 2026-08-09 19:21:54 +01:00
• c73affb3dc Only delete old context after emitting context changed wiht new context when inporting json nextpnr-0.11 Jasper Homann 2026-08-07 12:34:55 +02:00
• 9a4652e0f8 Protect json import with mutex Jasper Homann 2026-08-07 12:28:24 +02:00
• d3bbf4dc6e gui: Properly initialize himbaechel context when creating a new one during json import Jasper Homann 2026-08-07 12:26:04 +02:00
• de8cd9782f Accept UTF-8 filenames and terminal I/O on Windows. Catherine 2026-08-05 15:31:32 +00:00
• 8f6cab0fc8 gatemate: Place CC_MULT packed P register in same row (#1771) Jasper Homann 2026-08-06 00:49:49 +02:00
• 8d8053e0c5 xilinx: Make router2 default gatecat 2026-08-04 14:52:44 +02:00
• a3938de734 clangformat gatecat 2026-08-04 10:51:28 +02:00
• d324239345 xilinx: clean up some compiler warnings gatecat 2026-08-04 10:51:04 +02:00
• 049f38659a util: Replace use of strcasecmp in boolstr_or_default gatecat 2026-08-04 10:47:56 +02:00
• 44a4d1e6cd xilinx: don't use 'or' operator gatecat 2026-08-04 10:46:00 +02:00
• 0d4fffae10 Fix BaseArch::archId() gatecat 2026-08-04 10:40:26 +02:00
• 2fb1d1982f Gowin. Fix wire IDs leak. YRabbit 2026-08-03 18:40:25 +10:00
• 8945407874 docs/viaduct: don't reference nonexistent architecture in documentation Lunaphied 2026-08-02 19:58:30 +02:00
• 90b9be4859 router2: Fix ripup of constant nets gatecat 2026-08-01 15:43:10 +02:00
• 68c1acd80a fabulous: move timing-arc helpers to bel_timing.cc Jonas K. 2026-07-21 13:46:23 +02:00
• ef6931f440 fabulous: add generic way to set BEL timings and placer/router tunables Jonas K. 2026-07-16 12:27:10 +02:00
• 00376b6b0d qt: remove qt5 as it's no longer relevant and clean up some warnings Lunaphied 2026-03-27 16:22:26 +01:00
• 77e1f19f21 gatemate: fixed test assert Miodrag Milanovic 2026-07-27 14:52:21 +02:00
• bf63271fe7 ice40: Allow disablement of CE global promotion gatecat 2026-07-27 10:58:27 +02:00
• a6a6afa827 ice40: Add noglobal attribute and raise promotion threshold gatecat 2026-07-24 10:55:23 +02:00
• 498f0422cd himbaechel: Merge all test entrypoints into one gitRaiku 2026-06-30 13:57:36 +03:00
• bf80306e97 nexus: Fix OSHX primitives gatecat 2026-07-27 10:51:33 +02:00
• fb95bb8ea1 gatemate: Fix DFF pin names when packing mult p registers (#1755) Jasper Homann 2026-07-24 15:06:38 +02:00
• a7b62d7cb8 nexus: Fix memory corruption due to rehash gatecat 2026-07-24 13:52:18 +02:00
• da46844ca6 nexus: Fix slow routing around DQSBUFs gatecat 2026-07-22 14:03:42 +02:00
• f8097c3127 nexus: Initial improvements to edge clock routing gatecat 2026-07-22 13:55:15 +02:00
• c2cbdc7efa nexus: Initial support for DDR3 memory interfaces gatecat 2026-07-19 17:24:32 +02:00
• ddc6c8c8b9 nexus: Place ECLK bels gatecat 2026-07-19 10:46:49 +02:00
• 5eddc52881 nexus: Add other IODDR modes gatecat 2026-07-18 14:11:24 +02:00
• 02d57cfaa1 nexus: Add mapping for IDDRX2 gatecat 2026-07-18 13:50:27 +02:00
• 452e75bad6 nexus: Add a mapping for ODDRX2 gatecat 2026-07-18 13:35:13 +02:00
• ab65039755 nexus: Add ECLK bels gatecat 2026-07-18 13:09:37 +02:00
• 60ee033cca ci: Bump prjoxide version gatecat 2026-07-18 12:24:36 +02:00
• 1831ce9510 nexus: Add DQS routing to BBA gatecat 2026-07-18 11:45:24 +02:00
• 7c667eeba3 ecp5: Prioritise ECLK usage when placing PLLs gatecat 2026-07-16 13:05:27 +02:00
• 8624a48bcf ecp5: Make fabric routed ECLK an error gatecat 2026-07-16 12:10:35 +02:00
• 261152be8a ecp5: IDDRX2F has ALIGNWD too gatecat 2026-07-14 14:53:17 +02:00
• 4c72cee9ee gatemate, ng-ultra: add micko and I as code owners (#1747) Lofty 2026-07-12 11:43:35 +01:00
• fc9e96a6e6 python: Fix binding for getNetinfoRouteDelay gatecat 2026-07-12 11:39:41 +02:00
• 9f441ba455 fix association of BRAM port to clock in SDP mode (#1746) Michael OffelandMiO 2026-07-12 11:29:43 +02:00
• 7086ca791e WIP: static: improve region constraint handling gatecat/gatemate-part gatecat 2026-06-21 09:53:14 +02:00
• 47d88a6aa7 gatemate: Initial partitioning impl gatecat 2026-06-19 10:03:14 +02:00
• 8ec393fd47 gatemate: Import old hypergraph code gatecat 2026-06-18 13:29:00 +02:00
• 2b560ad0cc clangformat gatecat 2026-06-19 09:13:08 +02:00