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gatemate: Also use clock router for RAM clocks 

Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2026-08-12 11:20:17 +02:00 committed by myrtle
parent 51e703d094
commit c6eca2405b
1 changed files with 6 additions and 1 deletions
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7
himbaechel/uarch/gatemate/route_clock.cc
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@ -56,6 +56,11 @@ void GateMateImpl::route_clock()
return (ctx->getBelBucketForCellType(port.cell->type) == id_CPE_FF) && port.port.in(id_CLK_INT);
};
auto feeds_ram_or_iosel_clk_port = [&](PortRef &port) {
return (ctx->getBelBucketForCellType(port.cell->type).in(id_RAM_HALF, id_IOSEL)) &&
port.port.in(id_CLOCK1, id_CLOCK2, id_CLOCK3, id_CLOCK4);
};
auto feeds_ddr_port = [&](NetInfo *net, PortRef &port) {
return this->ddr_nets.find(net->name) != this->ddr_nets.end() && port.port == id_D0_10;
};
@ -120,7 +125,7 @@ void GateMateImpl::route_clock()
auto sink_wires = dict<WireId, PortRef>{};
auto sink_wires_to_do = pool<WireId>{};
for (auto &usr : clk_net->users) {
if (!feeds_clk_port(usr) && !feeds_ddr_port(clk_net, usr))
if (!feeds_clk_port(usr) && !feeds_ddr_port(clk_net, usr) && !feeds_ram_or_iosel_clk_port(usr))
continue;
auto sink_wire = ctx->getNetinfoSinkWire(clk_net, usr, 0);