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390 Commits 9 Branches 4 Tags 14 MiB
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64 Commits

Author SHA1 Message Date
Fischer Moseley e0aeb38cdb update docs 2024-03-07 12:25:30 -08:00
Fischer Moseley 0b2c286075 pull latest from main 2024-03-06 11:31:35 -08:00
Fischer Moseley 25ebae42e2 add GateMate ILA to alternatives 2024-03-03 13:57:52 -08:00
Fischer Moseley 6aea5cc6e1 update MemoryCore references 2024-03-02 12:52:04 -08:00
Fischer Moseley a4d549f6f1
update static site to match README formatting 2024-02-29 15:20:11 -05:00
Fischer Moseley 75a0fe46ff fix PLL information in Ethernet docs 2024-02-10 01:13:11 -08:00
Fischer Moseley 63e912fb63 fix grammar and diagrams 2024-02-09 22:49:58 -08:00
Fischer Moseley 510bae6f38 add MATLAB fpga data capture to alternatives, thanks nathan 2024-01-22 00:03:54 -08:00
Fischer Moseley b8de6339aa adjust some ergonomics found while playtesting 2024-01-21 00:23:07 -08:00
Fischer Moseley 2b95fea496 update docs, bump required python to 3.8 2024-01-13 15:05:45 -08:00
Fischer Moseley ee4a3026af refactor to use common bus layout across all modules 2024-01-07 18:17:09 -08:00
Fischer Moseley e2daf94f3f remove unneeded diagram 2024-01-05 23:43:47 -08:00
Fischer Moseley 89f1dcde1c convert diagrams to .drawio.svg format 2024-01-05 23:01:57 -08:00
Fischer Moseley a1130e8424 update docs in response to feedback from Joe 2023-09-11 19:09:42 -07:00
Fischer Moseley dbdb379c56 update docs with GitHub Actions config 2023-09-11 09:47:09 -07:00
Fischer Moseley 1e30f70a97 fix (another) typo in io_core example 2023-09-04 23:10:18 -04:00
Fischer Moseley c6dc1af6f2 fix typo in io_core example 2023-09-04 23:09:53 -04:00
Fischer Moseley 3ce8594247 update docs with new IO core options 2023-09-04 23:03:49 -04:00
Fischer Moseley 3fe95b75d8 upate image names 2023-09-02 09:54:20 -07:00
Fischer Moseley 63760adef9 fix broken links 2023-09-02 09:33:42 -07:00
Fischer Moseley c436873296 fix images on docs site 2023-09-02 09:29:26 -07:00
Fischer Moseley 245ff33b0a move roadmap to github issues 2023-09-02 11:39:16 -04:00
Fischer Moseley f60ec0c0e3 finish most of docs ahead of v1 2023-09-02 11:39:16 -04:00
Fischer Moseley f902d07b1d update read responses to use D as preamble 2023-09-02 11:39:16 -04:00
Fischer Moseley 6401ab6020 update bram docs 2023-09-02 11:39:16 -04:00
Fischer Moseley 833c3e5ca5 one last doc change 2023-09-02 11:39:16 -04:00
Fischer Moseley d497f80d2a logic analyzer docs 2023-09-02 11:39:16 -04:00
Fischer Moseley 7340ccbbcb more docs 2023-09-02 11:39:16 -04:00
Fischer Moseley 6d3a32a988 update lots of docs 2023-09-02 11:39:16 -04:00
Fischer Moseley 6aa27e431e build examples on self-hosted runner 2023-09-02 11:39:16 -04:00
Fischer Moseley c76a6de585 fix broken link in io core tutorial 2023-09-02 11:39:16 -04:00
Fischer Moseley 86e491b432 update io core example 2023-09-02 11:39:16 -04:00
Fischer Moseley 7ed4a9e6b8 polish uart testbenches 2023-09-02 11:39:16 -04:00
Fischer Moseley 0132d8fab0 update roadmap 2023-09-02 11:39:16 -04:00
Fischer Moseley d580419a5b remove lut_mem, clean up examples 2023-09-02 11:39:16 -04:00
Fischer Moseley d67ac9c799 add thesis pdf 2023-07-06 22:28:49 -07:00
Fischer Moseley 9c5ea31d14 enforce consistent naming of lut_mem module 2023-04-28 14:57:36 -04:00
Fischer Moseley 7cd8a2cfa5 tidy up mac stack 2023-04-28 14:57:36 -04:00
Fischer Moseley 28f40f2b7b add working l2 send in hardware 2023-04-28 14:57:36 -04:00
Fischer Moseley 6869ae631e docs hotfix during beta testing 2023-04-18 17:28:01 -04:00
Fischer Moseley 0268572779 update tutorial_1 2023-04-18 13:55:40 -04:00
Fischer Moseley af5d3a9b4b initial commit tutorial 2 2023-04-18 12:42:39 -04:00
Fischer Moseley 357b7eed94 refactor logic analyzer a little, add ps2_decoder example, and implement trigger_loc 2023-04-18 01:06:39 -04:00
Fischer Moseley 5172cab555 update todo 2023-04-17 18:14:31 -04:00
Fischer Moseley 870d299c74 add docs and add trigger config for logic analyzer 2023-04-17 18:14:31 -04:00
Fischer Moseley a2ad90a66a modify sim and generator, seems to work in simulation 2023-04-17 18:14:31 -04:00
Fischer Moseley a4c82ebb96 update docs site outline 2023-04-12 20:55:50 -04:00
Fischer Moseley 36f9791f4d update design philosphy in docs 2023-04-12 11:55:53 -04:00
Fischer Moseley ba6100ce30 import tutorial from yesterday, add mostly working bram core 2023-04-12 11:47:50 -04:00
Fischer Moseley 621ca48ad3 update deadlines in todo page 2023-04-04 00:28:15 -04:00