Fischer Moseley
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7cd8a2cfa5
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tidy up mac stack
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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c507f795f1
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add ethernet_tx/rx, semi-working in hardware
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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357b7eed94
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refactor logic analyzer a little, add ps2_decoder example, and implement trigger_loc
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2023-04-18 01:06:39 -04:00 |
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Fischer Moseley
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07624d83ee
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move back to iverilog 13 compatability
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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925fd915be
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update simulation syntax for iverilog 11 compat
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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1aa067b435
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update logic_analyzer_tb to use only generated HDL
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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a2ad90a66a
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modify sim and generator, seems to work in simulation
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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bdca8e01e7
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add boilerplate for new modules - just gotta rewrite the fsm
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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153ae7e3df
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video sprite example working! kinda frankensteined tho
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2023-04-13 17:02:55 -04:00 |
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Fischer Moseley
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5ceefc8da9
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this bram core has taken my soul
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2023-04-12 18:15:50 -04:00 |
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Fischer Moseley
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ba6100ce30
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import tutorial from yesterday, add mostly working bram core
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2023-04-12 11:47:50 -04:00 |
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Fischer Moseley
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3731305f63
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keep tidying bram core
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2023-04-10 18:03:02 -04:00 |
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Fischer Moseley
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db76ce3579
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reasonably tidy BRAM core - might be dependent on icarus 13
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2023-04-10 17:51:43 -04:00 |
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Fischer Moseley
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4837b2787a
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add (half) working BRAM core example
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2023-04-10 17:02:48 -04:00 |
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Fischer Moseley
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12f498dc9a
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add cursed BRAM core implementation
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2023-04-10 14:38:29 -04:00 |
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Fischer Moseley
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1710da6f87
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update makefile to represent new functional sim locations
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2023-04-09 22:33:58 -04:00 |
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Fischer Moseley
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353be7551e
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remove all narly verilog from python! 🤠
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2023-04-08 16:23:02 -04:00 |
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Fischer Moseley
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c604614428
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autogenerate logic_analyzer and sample_mem
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2023-04-03 23:15:09 -04:00 |
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Fischer Moseley
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0a4a1519c4
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clean up inferred BRAM, trim whitespace
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2023-04-03 21:20:58 -04:00 |
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Fischer Moseley
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8f08dffc70
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consolidate logic analyzer testbench
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2023-04-03 12:20:24 -04:00 |
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Fischer Moseley
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aea5a77258
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blacken autogen test runner
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2023-04-02 20:38:34 -04:00 |
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Fischer Moseley
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df4d243b9a
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refactor test structure
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2023-04-02 20:33:50 -04:00 |
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Fischer Moseley
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af295ead51
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logic analyzer appears to kinda work in simulation. buggy, but working!
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2023-04-02 13:54:34 -04:00 |
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Fischer Moseley
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edf94c9cf7
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add api generation tests
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2023-03-24 10:34:15 -04:00 |
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Fischer Moseley
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d5dfd3bbf3
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add boilerplate for API generation tests
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2023-03-23 23:50:09 -04:00 |
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Fischer Moseley
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2c51aa9a9a
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paritally imnplement io core autogeneration
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2023-03-16 09:38:17 -04:00 |
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Fischer Moseley
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11495fca61
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refactor logic analyzer into submodules
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2023-03-15 22:43:21 -04:00 |
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Fischer Moseley
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fade794333
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add initialls logic_analyzer core
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2023-03-15 15:57:42 -04:00 |
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Fischer Moseley
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aa2ba43e8f
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rename lut mem to lut ram, add to manta generator
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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5e2f02ebd6
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add linting to makefile, update bus testbenches
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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4d9792702a
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clean up testbenches, add Makefile for sims
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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e022696b31
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add working example for macOS bug
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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a70ba2d0a8
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replace uart modules with zipcpu for testing, TX seems to misalign itself
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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70e2bd10e7
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rename, slightly patch bridge_tx
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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70154f6904
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add uart_rx module, bus seems to be working end-to-end
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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5454ed37e9
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add bus_tb, has nearly all of manta end-to-end
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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c1620871cf
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add lut memory and tests, still need to sort out pipelining
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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e55d919098
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add in bus architecture prototypes from the last few days
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2023-03-14 16:24:56 -04:00 |
Fischer Moseley
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523b5673bc
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rename ila tests
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2023-02-09 15:31:32 -05:00 |
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Fischer Moseley
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d2bcbe2418
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import from openILA
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2023-02-04 12:43:00 -05:00 |