c0c838f1bc
Logic devices now working again
2008-07-29 12:11:44 +01:00
1a45e9164f
Find signal a logic device is connected to
2008-07-29 12:04:40 +01:00
8a5f129e56
Draw nexus in multiple passes
2008-07-29 12:00:26 +01:00
65c2ceb89d
Build entity hierarchy in separate stages
2008-07-29 11:01:02 +01:00
7a2e9c02cd
Simplify support function emitting code
2008-07-28 22:48:21 +01:00
f88415b1d7
Conversion of std_logic to integer
2008-07-28 22:46:39 +01:00
1250010696
Merge branch 'vhdl' of git@github.com:nickg/iverilog into vhdl
...
Conflicts:
tgt-vhdl/support.cc
2008-07-28 21:47:37 +01:00
506a0ba7d6
Support repeat in concatenation
2008-07-28 21:46:19 +01:00
1d4914c590
Undo last commit
2008-07-28 13:04:30 +01:00
3e28a10676
Compress support function names a bit
2008-07-28 13:02:04 +01:00
78028a3310
Fully support ternary expressions
2008-07-28 12:59:10 +01:00
b9cecbef64
Make sure LPM comparison result is std_logic not Boolean
2008-07-27 19:05:49 +01:00
8b32096e2a
Convert std_logic to Boolean in loop tests
2008-07-27 18:39:16 +01:00
ba462eb8b7
Merge branch 'vhdl' of git@github.com:nickg/iverilog into vhdl
2008-07-25 20:00:26 +01:00
5a09819729
Catch case of select expression on non-variable
2008-07-24 16:00:12 +01:00
d3296d4895
Refactor while/for loop code to use common base
2008-07-24 15:22:25 +01:00
39c9c54760
Add repeat statement
2008-07-24 14:52:06 +01:00
8bee5b1108
Add `forever' statement type
2008-07-24 14:30:10 +01:00
e4c2400eb2
Refactor the expression->time code into a single function
2008-07-23 16:18:49 +01:00
1409207def
Correctly indent case statements
2008-07-23 14:31:41 +01:00
30fdadc525
Support delays in logic devices
2008-07-23 13:40:42 +01:00
a5db0297b0
Unary minus
2008-07-22 15:44:29 +01:00
e25f946ac0
Merge branch 'vhdl' of file:///media/disk/data/iverilog/ into vhdl
2008-07-21 15:20:42 +01:00
2f4f075005
Typo
2008-07-21 15:20:40 +01:00
3ca85491ee
Unary AND and XOR
2008-07-20 16:41:57 +01:00
d8351ec1b2
Fix reduction OR in procedural code
2008-07-20 15:13:20 +01:00
77508b9afa
Reduction OR operator
2008-07-20 15:10:00 +01:00
38de6ebf3a
Compress support function definitions a bit
2008-07-19 21:04:52 +01:00
af3ee49f57
Refactor support function code a bit
2008-07-19 20:49:55 +01:00
0cb6ea34d7
Move type conversion code into a separate file
2008-07-19 15:23:47 +01:00
b6df73d3b9
Support functions for converting (un)signed -> boolean
2008-07-19 15:15:16 +01:00
2d79e1a2e0
Store the currently active entity
2008-07-19 14:45:00 +01:00
7b311b6adb
Translate internal delays in assignments
2008-07-18 14:47:35 +01:00
df4a380e42
Fix implementation of IVL_LPM_UFUNC
...
Function name was not correct.
2008-07-18 14:31:12 +01:00
6ff80e80a4
Catch case where (un)signed is converted to boolean
2008-07-18 12:30:24 +01:00
8b6b111541
Add IVL_LPM_CMP_EQ
2008-07-18 11:58:26 +01:00
fd8f01e317
Add IVL_LPM_CMP_GE
2008-07-18 11:56:00 +01:00
00317dd47f
Dummy implementation of $time
2008-07-18 11:50:05 +01:00
e9637f6d11
Generate synthesisable code for sequential processes
...
Whilst adding `wait until ...' at the end of every
process is a valid translation of the input, it is not
actually synthesisable in at least one commercial
synthesiser (XST). According to the XST manual the
correct template is to use `wait until ...' at the
start of sequential processes and `wait on ...'
(equivalent to `wait until ...' with 'Event on all
the signals) at the end of combinatorial processes.
This patch implements that.
2008-07-17 17:36:42 +01:00
1f9ed2c5ec
VHDL AST element for `wait on' statement
2008-07-17 17:23:21 +01:00
7677b59650
Make sure offset of IVL_LPM_ARRAY is integer
2008-07-17 16:41:34 +01:00
9cf4792d53
Translate array references in expressions
2008-07-17 14:47:10 +01:00
4d9f029000
Generate correct array bounds
2008-07-17 14:38:07 +01:00
9916686c24
Convert constant bits to integers
2008-07-17 14:29:56 +01:00
c86377790f
Automatically convert constant bit strings to integers
2008-07-17 14:26:35 +01:00
2a791bfb38
Assignment to arrays
2008-07-17 13:41:44 +01:00
1d3ac6bc1f
Generate VHDL array type declarations of Verilog arrays
2008-07-17 13:08:55 +01:00
3fa5a04947
Merge branch 'vhdl' into array
2008-07-17 12:01:09 +01:00
7c5b0f737c
Class for VHDL type declarations
2008-07-17 11:59:02 +01:00
c116808fdb
Remove duplicated code
2008-07-17 11:46:36 +01:00
Nick Gasson