d997397c38
Generate function calls with parameters
2008-06-25 21:49:22 +01:00
7773000c36
Generate function declarations
2008-06-25 21:40:35 +01:00
042f7ccbcd
Generate a return type for functions
2008-06-25 18:43:50 +01:00
44aa8a6b91
Associate signals with scopes rather than entities
2008-06-25 18:12:57 +01:00
43c671cb5c
Emit VHDL for function declarations
2008-06-25 18:00:48 +01:00
a3df37b851
Initial code to generate function calls
...
Also catch a few null-pointer issues
2008-06-25 17:29:09 +01:00
c01c2bd742
Dummy code for handling function scopes
2008-06-25 12:48:46 +01:00
533ee87bb1
Delay elaborate of instance array scopes to allow defparams to propagate.
...
When we detect that a module instance is an array of instances, delay
the elaboration of the array until after the first defparam processing
is complete. This allows for defparam statements to control the
instantiation of module instance arrays.
2008-06-24 22:03:28 -07:00
c810406195
run scope elaboration as queued work items.
...
Putting scope elaboration into work queue items allows for handling
more complex processing order. The elaboration_work_list queue drives
the processing of elaborate_scope and parameter evaluation.
2008-06-24 20:28:08 -07:00
3ec8a867db
Spelling fixes
...
comments, documentation, a variable name, and a couple of messages
2008-06-24 17:01:45 -07:00
899a70908e
Fix small bug with initialisation and ammend comments
2008-06-24 20:13:18 +01:00
bf95d77562
Finish replacing vhdl_process with vhdl_procedural
2008-06-24 20:01:06 +01:00
db992e808f
Start using vhdl_procedural instead of vhdl_process
2008-06-24 19:54:22 +01:00
f2aca68b82
Add new vhdl_procedural superclass for process/task/func
2008-06-24 19:50:57 +01:00
12b448ef01
Merge branch 'vhdl' of git@github.com:nickg/iverilog into vhdl
...
Conflicts:
tgt-vhdl/vhdl_syntax.cc
2008-06-24 19:42:35 +01:00
e77bb0157e
Remove redundant methods from vhdl_arch
2008-06-24 19:39:05 +01:00
75631bd8f1
Move is_inital code out of vhdl_process into vhdl_scope
...
Part of tidy up before implementing functions
2008-06-24 19:06:06 +01:00
63b1887ff2
Refactor code to use the new vhdl_scope class
2008-06-24 18:52:25 +01:00
ba36e47575
Add new vhdl_scope class and refactor
2008-06-24 18:12:00 +01:00
3866c4526e
Simplify code to emit operators
2008-06-24 14:58:58 +01:00
cb08f02de1
Resize signed/unsigned bit vectors correctly
2008-06-24 10:58:21 +01:00
4188fbecee
Add XOR operator and catch default case branch
2008-06-24 10:55:45 +01:00
f261bf7e97
Fix bug where variables could be declared twice
2008-06-23 15:13:10 +01:00
88dc9b6b63
Remove debugging information from the output
2008-06-23 15:02:26 +01:00
632a265e14
Fix casting/resizing order bug
2008-06-23 15:00:55 +01:00
449cd0a76e
Correctly generate signed/unsigned types
2008-06-23 14:28:27 +01:00
181a53d3ed
Merge branch 'master' of git://github.com/steveicarus/iverilog into vhdl
2008-06-23 13:48:56 +01:00
44958409f5
A slightly smarter $display
2008-06-23 13:45:24 +01:00
f81129aa68
Fix some bugs with blocking assignment
2008-06-23 13:36:28 +01:00
e5ef0d97bd
Fix signed/unsigned resizing
2008-06-23 13:04:28 +01:00
469036990a
Output blocking assignments in the right place
2008-06-23 12:30:48 +01:00
d06f5c7c54
Emit loop statements with the correct indent
2008-06-23 12:27:30 +01:00
9911939576
Simplify casting code
2008-06-23 12:21:10 +01:00
c9ace14c40
Shift operators working correctly
2008-06-23 12:14:12 +01:00
d5cdb91d55
Handle complex expressions in case statement
2008-06-23 11:36:12 +01:00
360be597a8
Minor cleanup and comments.
...
The initial elaboration needs better comments/documentation.
2008-06-21 18:36:46 -07:00
75f7c9ae0c
Only move constant assignments into initialisation
2008-06-21 16:40:18 +01:00
c926454a41
Statements might be emitted in wrong order
2008-06-21 16:33:05 +01:00
5cfe7ea0aa
Tidy up output
2008-06-21 16:28:07 +01:00
c70fb4ba08
Simple implementation of IVL_EX_SELECT
2008-06-21 16:17:44 +01:00
7cba9f3cb2
Shift left/right
2008-06-21 15:19:33 +01:00
d6acb8d059
Less than / greater than
2008-06-21 15:16:22 +01:00
ec23b70bb7
While loops
2008-06-21 15:13:44 +01:00
58f2f5007d
Bitwise AND
2008-06-21 15:05:48 +01:00
0caf4fd9d0
Add case statement
2008-06-21 15:03:36 +01:00
037ce08f72
Fix tiny bug in $display code
2008-06-21 14:42:54 +01:00
27cdd27889
Add .cast/int and update .cast/real.
...
This patch adds .cast/int and updates .cast/real to act as a local
(temporary) net and to support either a signed or unsigned input.
The vvp_vector4_t class not can convert an arbitrarily sized double
to a vector value. This removes the restriction of lround().
Also document the new statements.
2008-06-20 19:45:18 -07:00
f60a6561bb
Cast strlen to int for printf field width
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strlen is a size_t, and the * field width takes an int.
Make this an explicit cast. It's good for 64-bit machines
and squelches warnings from gcc-4.3.
2008-06-20 15:54:32 -07:00
204862ac3c
Implement $write
2008-06-20 19:00:07 +01:00
0f50849fbb
Add call to To_Integer when printing signed/unsigned
2008-06-20 18:26:39 +01:00
Nick Gasson
Stephen Williams
Larry Doolittle
Cary R