This patch introduces in ScopeBase separate containers
for declarations coming from the current scope and from
the previous scopes.
Until now, in one scope, all objects were kept in an stl map.
When a scope was created inside other scopes, a shallow
copy of the map was made. This solution was nice for
name shadowing (in new scopes, when a name was
encountered, the old objects were overridden by a new
one), but didn't allow for distinguishing where the objects
were allocated. As a result, it is impossible to know who
the owner is and who should delete them.
In this commit ScopeBase gets two containers: for old
and new objects. If a ScopeBase is made from another
ScopeBase object, all objects from the copied object
go to an old_XXX container, where XXX depends on the
type of the copied objects. When a ScopeBase object
is deleted, the objects from new_XXX are deleted and
the ones from old_XXX are not touched.
This patch adds some complexity to the internals
of ScopeBase, but leaves its interface unchanged.
This is rather a cosmetic change. The patch changes
the container used for stack of scopes from std::list
to std::stack. It suits this particular application
a bit better.
Thanks to valgrind analysis it turned out that
there were objects in the parser that were not being
deleted in a proper way. This patch fixes them all.
Instead of using automatic variables for global
types, I allocate them dynamically. Thanks to it,
all type objects can be treated in the same way,
as all of them are pointers allocated with `new'.
Now we will be able to remove all scopes in the same
manner, no matter if it is a global or local scope,
by deleting all carried pointers.
When writing arrays to the work library, handle the special
case that it is an array of std_logic and write a std_logic_vector
declaration instead. This makes for a more compact description.
When a "use" clause tries to pull a package from the work library,
put together a file name and try to find that package in the
work library directory. If found, parse the package file and
try again to find the package.
Bison and Flex generate different interfaces for reentrant
parsers, so handle that different API. We need this change
because library support is going to reuse the parser to
read in library packages.
This patch adds code to check for a negative or undefined value used in
an enumeration sequence name, it verifies that the count in an enumeration
sequence name is not zero and allows more decimal constant values in the
enumeration sequence name..
isprint() is defined to take an int and if it is defined as a macro then
you can get a warning that a char is being used as an array index. This
patch fixes this warning in tgt-vlog95/msic.c
SystemVerilog extended the assignments operator support to C-like
assignment operators and special bitwise assignment operators.
For example:
a += 1;
a -= 1;
The list of these operators can be found in SV LRM (1800-2009)
section 11.4.1.
NOTE: I fixed a few parts of this. In particular, the PEBShift
class is used for shift operators.
Acked-and-Tested-by: Oswaldo Cadenas <oswaldo.cadenas@gmail.com>
Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
This function is for the time being used in the
component instatiation. It is checked, whether
an expression is a correct r-value.
To be a correct r-value, it must be either
port name or signal name.
pow(int, int) is ambiguous since it could use the double version from
the math library or the verinum version. This patch makes it obvious that
we want to use the double version.
Build up a work library by writing a VHDL representation of the
package header into a source file. This representation needs to
be accurate enough that later invocations of vhdlpp can read them
with the VHDL parser.
SystemVerilog has support for time literals. The time literal for
example #10ns, adds a delay of 10ns no matter the time unit currently
in effect. For more details please refer to
http://iverilog.wikia.com/wiki/Projects#SystemVerilog_Style_Time_Literals
Tested-by: Oswaldo Cadenas <oswaldo.cadenas@gmail.com>
Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
A bit/logic output type in a module initially is defaulted to as a
variable. Depending on how they are used in the module, the type
changes accordingly.
For example
module test(output logic l);
assign l = '0;
endmodule
The variable 'l' would be promoted to a Net data type, when the
'assign' statement is encountered.
Acked-by: Oswaldo Cadenas <oswaldo.cadenas@gmail.com>
Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
The module declaration should allow initialization of the bit and
logic data types.
For example:
$ cat clkgen.sv
module clkgen(output logic clk = 0, output bit p = 1);
initial begin
#200;
$display("p = %b", p);
$finish;
end
initial forever #10 clk = ~clk;
endmodule
$ iverilog -g 2009 clkgen.sv
$ ./a.out
p = 1
Suggested-by: Oswaldo Cadenas <oswaldo.cadenas@gmail.com>
Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
SystemVerilog allows passing the 'bit' and 'logic' arguments to a
function. The patch adds support for parsing these function
definitions. The 'bit' data type is treated as boolean, whereas 'logic'
data type remains as logic.
Acked-by: Oswaldo Cadenas <oswaldo.cadenas@gmail.com>
Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
This patch removes the space between -L and the directory in the vpi
Makefile. It also fixes the line to use the correct variable name
for the LDFLAGS.
The patch allows parsing of function definitions which do not have
explicit data type or range. The default return data type is assumed
to be reg unsigned and the default range is 0.
Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
Verilog allows returning variables of 'reg' type. The icarus verilog
implicitly assumes the default returned type of the function as
'reg unsigned'. The patch allows to explicitly specify the 'reg' return
type.
Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
Verilog allows user to define variables of primitive types. The patch
adds support for defining variables of type 'logic'. The data type
'logic' is the only primitive data type which supports defining ranges.
Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
Verilog allows user to define variables of primitive types. The patch
adds support for defining variables of type 'bit'. The data type 'bit'
is the only primitive data type which supports defining ranges.
Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
Remove an unused variable (desired_vector_width) in elaborate.cc.
Reduce the scope of spin to make it obvious it is only used locally
in elaborate.cc. Initialize sel_type_ in the NetAssign_ constructor
(net_assign.cc). The code doesn't currently require this since
sel_type_ is only used when the base is not zero and it is always
defined when base is not zero, but giving this a default value in
the constructor hedges against accidentally using an undefined
value if someone checks the select type when the base is zero.
The $ivlh_attribute_event system function helps the Verilog runtime
support <name>'event expressions in VHDL. The vhdlpp generates a
call to $ivlh_attribute_event, which in turn uses callbacks to handle
the support.
This is also the start of the vhdl_sys vpi module. This module should
by included whenever VHDL code is parsed.
The compiler was handling bi-directional pass switches using the default
case for primitive gates, where the first port is treated as an output
and the remaining ports are treated as inputs. This patch adds a special
case for pass switches, so that the first two ports are treated as
bi-directional.
Pawel Szostek
Stephen Williams
Cary R
Prasad Joshi
Martin Whitaker