If the right hand operand of a shift is a signed vector value, it
is coerced to an unsigned value. This needs to be allowed for when
estimating the width expansion caused by a shift in a lossless
expression.
The power operator defines 2**-1 and -2**-1 to be zero. This patch fixes
both the procedural and continuous assignments to work correctly. It also
fixes a problem in the compiler power code so that the one constant value
always has at least two bits.
This patch adds support for calculating the queue mean inter-arrival
time. This is just the latest add time minus the first add time
divided by the number of intervals (the number of adds minus one).
This patch adds full support for the stochastic tasks/functions except
the mean inter-arrival and average wait statistics are not currently
available. These will be added in a later patch. This implementation
goes a bit beyond the standard and supports the following:
1. The job and inform arguments support 32 bit four state values.
2. The id for all routines, the job and inform arguments for $q_add(),
the statistic code for $q_exam() along with the queue type and
maximum length arguments for $q_initialize() can be less than or
equal to 32 bits. The argument will be sign extended if needed to
fill the internal 32 bit value.
3. The job and inform arguments to $q_remove() and the status argument
for all the routines must be 32 bits, but do not have to be an
integer variable (e.g. a 32 bit register or part select is OK).
4. An undefined bit in the id argument for any of the routines will
return a status of 2 (undefined queue id). Undefined bits are not
automatically converted to zero.
5. Undefined bits in the $q_initialize() queue type and maximum
length arguments or the $q_exam() statistic code argument are also
flagged as an error (are not converted to zero).
6. The $q_full() function returns 2 on error, the other routines that
return a value $q_remove() job/inform arguments and the $q_exam()
statistic value argument will usually return x on error.
7. An invalid statistic code will set the $q_exam() status to 8.
8. The $q_exam() statistic value argument can be 32 bits or larger.
This allows returning large statistical time values.
9. All time values are internally saved in simulation time units.
They will be converted to the calling module's time unit (with
rounding) before they are returned.
10. If a $q_exam() statistical value is too large to fit into the
variable the maximum positive value will be returned and the
status code will be set to 9 (value is too large).
11. If a statistical value is currently undefined $q_exam() will
return 10 (no statistical information) (e.g. using code 5 on an
empty queue).
This patch allows the compiler to perform early elaboration
of functions if they are encountered in expressions that are
elaborated before the function would normally be elaborated.
This makes the function available for constant evaluation.
Suitable error messages are generated if a function that is
used in a constant expression is not a valid constant function.
For now Icarus doesn't support a UDP instantiation with a range.
Instead of generating a warning about the port count being wrong
this patch adds code to calculate the range and print a message
if a range greater than one is found.
This creates the Package class to represent packages, and the
Scope class to represent scopes in general. The library functions
are worked up to support scanning scopes for declarations that are
imported by "use" clauses.
Make sure in a conponent instantiation that the instantiated
component is really declared, and that the ports of the binding
really do match the ports of the declared component. This requires
that we create and save component declarations, and that components
have methods for mapping the ports.
Certain types of expressions involving only constants would produce
ambiguous VHDL output. Fixed by qualifying one of the arguments. E.g.
('0' or '1') = '1'
Which is ambiguous becomes
(std_logic'('0') or '1') = '1'
This fixes the xnor_test test.
Reduce XNOR was implemented incorrectly because of trivial typo
Fixes regression of simple_gen test.
Also extended ivl_lpm_size API call to support all LPM types. This
simplifies some of the VHDL LPM generation code a little.
When a user or system function is called on the RHS of a continuous
assignment, and one of the function arguments is an undeclared
identifier, the compiler reports the error correctly but then
crashes. This patch fixes the crash.
This patch changes the method used to signal that a constant expression
is being elaborated from flags stored in global variables to flags
passed down the call chain. It also generates more informative error
messages when variable references are found in a constant expression.
There has been added additional default attribute to
all 'dump' function calls which is in all cases equal
to 0. Now one can specify how much this debug dumping should
be intended. This should allow people to dump smoothly whole
designs (as it was now) as far as separate units.
This is now the parent who specifies the base indentation
for all components (children). For example, architecture
"decides" how much their signals should be indented.
During elaboration, it is sometimes efficient to collapse a
collections of PV drivers to a net to a single concatenation.
This removes a bunch of resolutions and other nodes, and also
is the only way that 2-value logic should work.
During elaboration, it is sometimes efficient to collapse a
collections of PV drivers to a net to a single concatenation.
This removes a bunch of resolutions and other nodes, and also
is the only way that 2-value logic should work.
This gets us as far as emiting a component instantiation. Very little
error checking/elaboration is done, so there is room for improvement,
but this is a working stub.
This gets us as far as emiting a component instantiation. Very little
error checking/elaboration is done, so there is room for improvement,
but this is a working stub.
Up till now only "global" use clauses were parsed
and as a result libraries were loaded.
Since use clauses can appear not only in global context,
parsing of non-global clauses has been introduced and
selected names are now handled (like name1.name2.name3).
This gets us as far as emiting a component instantiation. Very little
error checking/elaboration is done, so there is room for improvement,
but this is a working stub.
These signals are declared in the architecture and are local to
the module. The Architecture already parsed and stored these signal
declarations, but this patch adds the ability to actually emit these
signals in the generated code.
In the process of doing this, I had to regularize the elaboration
and emit of VTypes, so that it can be used in multiple places, not
just in entity headers (for ports).
I also added support for bit selects of signals. This effected a couple
places in the parser, and expressions in general.
The bison grammar has been extended in order
to parse configuration statements. Parsing
remains very primitive but principal constructs
can be now recognized.
IEEE 1800-2005/9 says "each fixed-size dimension shall be represented by
an address range, such as [1:1024], or a single positive number to
specify the size of a fixed-size unpacked array, as in C. In other
words, [size] becomes the same as [0:size-1]."
This patch implements that translation in the parser. It issues a
warning when doing so when the generation flag is less than 2005-sv.
These signals are declared in the architecture and are local to
the module. The Architecture already parsed and stored these signal
declarations, but this patch adds the ability to actually emit these
signals in the generated code.
In the process of doing this, I had to regularize the elaboration
and emit of VTypes, so that it can be used in multiple places, not
just in entity headers (for ports).
I also added support for bit selects of signals. This effected a couple
places in the parser, and expressions in general.
This patch adds code to make sure a double (Verilog real) constant
is printed correctly. It also adds code to trim any leading escaped
NULLs from an expression string.
In VHDL it is allowed to have multiple architectures
per one entity. The proper architecture should be then
chosen in a configuration block. Now, if many architectures
will be found, then there will be a warning message printed.
FIXME notes are added in order not to forget about changes to
be done
This patch uses the new function (ivl_logic_is_cassign) to determine
if a logical was really the base of a continuous assignment. This
allows creating code that more closely matches the original.
This patch adds code that allows the targets to determine if a logical
gate came from a continuous assignment. This helps some of the targets
generate code that more closely matches the input.
It also reworks/simplifies the synthesis of && and || since the
compiler has already converted the two operands to single bit form
and fixes a mismatched delete from a previous patch.
This patch adds support for correctly handling most unconnected ports.
Most important is top level ports that are the root of the conversion.
This patch also adds support for emitting more signed constructs when
they are requested. $signed() and $unsigned() are still not supported
or recognized as an error when not emitting signed constructs.
Martin Whitaker
Cary R
Stephen Williams
Nick Gasson
Larry Doolittle
Pawel Szostek
Pawel Szostek
Jared Casper