This patch updates the $scanf and $printtimescale routines to work with
two-state variables. It also updates the general is_numeric check to
recognize two-state variables as numeric.
Modify the $random code to allow the seed to be either an int, long or
bit that is 32 bits or longer. The 32 bit check is new and also applies
to reg/logic variables.
This patch fixes a few more bugs in the enumeration code.
It add support for saving the file and line information to make
diagnostic messages better.
It updates some of the compiler warning messages to use the file
and line information.
It passes if the enumeration type is signed all the way to the
code generators.
It fixes the parser to correctly have the range after the signed
designation for the vector types.
It adds a warning that vvp does not currently support a negative
two state enumeration value.
We need to print a message and fail if the two \\ characters are not found
in the executable path.
Also update the generation warning to include -g2005-sv.
This is caused by a bug in some simple pattern matching the VHDL target does to try
and produce more idiomatic code in common cases (e.g. FFs with asynchronous resets in
this case). This patch just restricts the kinds of if-statements we use this
optimisation for.
The patch adds necessary error checking to verify that the operands of
increment decrement operator is not number.
Signed-off-by: Prasad Joshi <prasad@canopusconsultancy.com>
Type cast expressions and some function calls are syntactically
identical to array element select, so we can only tell the difference
by looking up the name of the identifier being selected. If it is a
type name, then create an ExpCast instead of an ExpName object.
Also, parse and emit vector part selects.
Add a new IVL_PR_FINAL process type.
Add a flag to NetScope in_final_ which is set when elaborating the
statement of a final procedure.
Add checks during statement elaboration for invalid statements in a
final procedure, similar to checks for statements in functions.
Do a final check to make sure no final blocks have delays.
In the vvp runtime, use "$final" as the flag for the thread created by
the final procedure. During compilation, instead of adding such a
thread to the sched_list, add it to a new schedule_final_list that
mirrors the schedule_init_list, but is run at the end of simulation.
This patch adds support for increment/decrement operators as an
expression. The operations on real and vector slices have been
disabled for now.
These operators can be used as in independent statements. However, the
corresponding support is not added in parser.
Changes since V2:
- Additional error checking in elaboration to deny operation on vector
slices and real (suggested by Martin)
Changes since V1:
- Use 'i' and 'I' for increment (suggested by Cary)
- Evaluate sub-expression once (suggested by Cary and Stev)
- Add necessary checks during elaboration to ensure that the
expression is valid (suggested Stev)
- Proper width handling with vectors (suggested by Martin)
Signed-off-by: Prasad Joshi <prasad@canopusconsultancy.com>
Icarus uses 'i' in the net expressions for a cast to integer. Replacing
it with 'v' would free the character 'i' that can be used for increment
operators. This changes cast operators to become 'v', '2', and 'r'.
Signed-off-by: Prasad Joshi <prasad@canopusconsultancy.com>
Suggested-by: Cary R. <cygcary@yahoo.com>
The vvp target code generator may not elide a BUFZ if the output of
the BUFZ is connected to a net that is the subject of a procedural
force statement.
Named libraries are similar to the work library, but they are not
written to implicitly, or imported implicitly. They are only brought
in by a "library" clause, the the packages within the library are
brought in by a "use" clause.
Technically the sized function is not currently needed by Icarus since
the SFT file handles this type of information, but lets define this so
that things work correctly if we ever switch to using the standard VPI
interface. Also mark this as a system defined function.
Presumably, the user will want the ability to explicitly set the
working library location, so create a +vhdl-work+ plusarg setting
for exactly that purpose.
Port map aspects were held in std::maps. Because
of that, in case of multiple assignments to the same
port, some assignments were lost and in effect vhdlpp
produced correct verilog code from a buggy VHDL.
Std::map was replaced by std::multimap. Thanks to it
we can gather this multiple assignments and detect them
in the elaboration phase.
Cary R
Nick Gasson
Stephen Williams
Prasad Joshi
Jared Casper
Martin Whitaker
Pawel Szostek