Nick Gasson
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b0de1a8d7e
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Implement part select for LHS of assignment
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2008-07-07 16:11:45 +01:00 |
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Nick Gasson
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c33600bcc3
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Add concatenation operator
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2008-07-06 18:21:34 +01:00 |
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Nick Gasson
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c54b36c902
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Add logical AND operator
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2008-07-04 11:10:20 +01:00 |
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Nick Gasson
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19cbab78b2
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Tidy up code to generate default branch of case
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2008-07-03 20:04:47 +01:00 |
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Nick Gasson
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930e04f6c7
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Ensure port map expressions are globally static
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2008-07-01 11:28:02 +01:00 |
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Nick Gasson
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050aa277ae
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Make vhdl_element::emit a little more generic
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2008-07-01 10:37:22 +01:00 |
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Nick Gasson
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081f397460
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Implement LPM part select
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2008-06-27 14:58:03 +01:00 |
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Nick Gasson
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fd60bfd3d2
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Rewrite function parameter finding code
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2008-06-27 12:18:39 +01:00 |
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Nick Gasson
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500442e5c5
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Working function calls
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2008-06-25 22:15:57 +01:00 |
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Nick Gasson
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43c671cb5c
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Emit VHDL for function declarations
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2008-06-25 18:00:48 +01:00 |
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Nick Gasson
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a3df37b851
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Initial code to generate function calls
Also catch a few null-pointer issues
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2008-06-25 17:29:09 +01:00 |
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Nick Gasson
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c01c2bd742
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Dummy code for handling function scopes
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2008-06-25 12:48:46 +01:00 |
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Nick Gasson
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899a70908e
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Fix small bug with initialisation and ammend comments
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2008-06-24 20:13:18 +01:00 |
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Nick Gasson
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bf95d77562
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Finish replacing vhdl_process with vhdl_procedural
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2008-06-24 20:01:06 +01:00 |
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Nick Gasson
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db992e808f
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Start using vhdl_procedural instead of vhdl_process
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2008-06-24 19:54:22 +01:00 |
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Nick Gasson
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f2aca68b82
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Add new vhdl_procedural superclass for process/task/func
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2008-06-24 19:50:57 +01:00 |
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Nick Gasson
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12b448ef01
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Merge branch 'vhdl' of git@github.com:nickg/iverilog into vhdl
Conflicts:
tgt-vhdl/vhdl_syntax.cc
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2008-06-24 19:42:35 +01:00 |
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Nick Gasson
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e77bb0157e
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Remove redundant methods from vhdl_arch
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2008-06-24 19:39:05 +01:00 |
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Nick Gasson
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75631bd8f1
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Move is_inital code out of vhdl_process into vhdl_scope
Part of tidy up before implementing functions
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2008-06-24 19:06:06 +01:00 |
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Nick Gasson
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63b1887ff2
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Refactor code to use the new vhdl_scope class
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2008-06-24 18:52:25 +01:00 |
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Nick Gasson
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ba36e47575
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Add new vhdl_scope class and refactor
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2008-06-24 18:12:00 +01:00 |
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Nick Gasson
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3866c4526e
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Simplify code to emit operators
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2008-06-24 14:58:58 +01:00 |
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Nick Gasson
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4188fbecee
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Add XOR operator and catch default case branch
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2008-06-24 10:55:45 +01:00 |
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Nick Gasson
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449cd0a76e
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Correctly generate signed/unsigned types
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2008-06-23 14:28:27 +01:00 |
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Nick Gasson
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e5ef0d97bd
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Fix signed/unsigned resizing
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2008-06-23 13:04:28 +01:00 |
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Nick Gasson
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c9ace14c40
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Shift operators working correctly
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2008-06-23 12:14:12 +01:00 |
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Nick Gasson
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75f7c9ae0c
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Only move constant assignments into initialisation
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2008-06-21 16:40:18 +01:00 |
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Nick Gasson
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c70fb4ba08
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Simple implementation of IVL_EX_SELECT
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2008-06-21 16:17:44 +01:00 |
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Nick Gasson
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7cba9f3cb2
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Shift left/right
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2008-06-21 15:19:33 +01:00 |
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Nick Gasson
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d6acb8d059
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Less than / greater than
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2008-06-21 15:16:22 +01:00 |
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Nick Gasson
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ec23b70bb7
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While loops
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2008-06-21 15:13:44 +01:00 |
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Nick Gasson
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0caf4fd9d0
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Add case statement
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2008-06-21 15:03:36 +01:00 |
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Nick Gasson
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d7bb5658f2
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Translate IVL_ST_DELAYX statements
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2008-06-19 12:16:19 +01:00 |
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Nick Gasson
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254ccb9ccb
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First passing at blocking assignment
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2008-06-18 13:06:27 +01:00 |
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Nick Gasson
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d2bebee9d9
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Refactor before adding blocking assignment
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2008-06-18 12:51:11 +01:00 |
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Nick Gasson
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af8c08e6a7
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Allow optional VHPI $finish implementation
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2008-06-17 20:16:16 +01:00 |
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Nick Gasson
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1debbc3100
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Simplify edge_detector() a bit
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2008-06-16 20:06:06 +01:00 |
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Nick Gasson
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8d0afa632d
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Subtraction and multiplication LPM devices
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2008-06-16 19:49:24 +01:00 |
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Nick Gasson
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ce72eb4eb4
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Fix Valgrind warnings
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2008-06-16 14:26:38 +01:00 |
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Nick Gasson
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7cde5f247e
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Add translation for not-equals operator
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2008-06-16 12:47:41 +01:00 |
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Nick Gasson
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919c1d695c
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Adding binary +
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2008-06-14 17:09:31 +01:00 |
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Nick Gasson
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9fbb449e06
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Optimise away empty (VHDL) processes
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2008-06-13 14:17:24 +01:00 |
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Nick Gasson
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be3c4cf268
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Generate signal initial values from `initial' processes
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2008-06-13 14:10:28 +01:00 |
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Nick Gasson
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0a8fd50c4a
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Find assignments that could be initializers
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2008-06-13 13:59:48 +01:00 |
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Nick Gasson
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0df3eabe26
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Convert `if (foo) ..' to `if foo = '1' then ..'
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2008-06-12 11:36:21 +01:00 |
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Nick Gasson
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8fe2211e2b
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Generate `after' modifier instead of `wait' statements
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2008-06-12 11:24:43 +01:00 |
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Nick Gasson
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7eb41304e6
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Generate rising/falling edge detectors
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2008-06-12 10:36:38 +01:00 |
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Nick Gasson
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a7cfdc3a87
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Add VHDL if statement to AST types
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2008-06-11 14:11:37 +01:00 |
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Nick Gasson
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b010b8e3ca
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Use `assert false' as initial translation of $finish
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2008-06-11 13:37:21 +01:00 |
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Nick Gasson
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26a2c69c2e
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Change architecture name to `FromVerilog'
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2008-06-11 11:31:43 +01:00 |