luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
4,495 Commits 23 Branches 234 Tags 41 MiB
Commit Graph

4495 Commits

Author SHA1 Message Date
Nick Gasson 7e999c5496 Fix continuous assignment of constants 
E.g. in assign p = 1 the RHS signal in the generated LPM now
has a correct intial value (and it will never be written to
elsewhere)
 2008-07-03 15:13:12 +01:00
Nick Gasson 4fac825457 Add PV part select type 2008-07-03 14:45:54 +01:00
Nick Gasson 35c66744db Cleanup and remove debug output 2008-07-01 11:31:00 +01:00
Nick Gasson 930e04f6c7 Ensure port map expressions are globally static 2008-07-01 11:28:02 +01:00
Nick Gasson 37756b8d06 Avoid mapping a signal to itself 2008-07-01 11:13:02 +01:00
Nick Gasson 596c93ce7e Rename instance if it has the same name as the type 2008-07-01 11:05:24 +01:00
Nick Gasson edfae1abfb PV LPM part select type 2008-07-01 11:02:49 +01:00
Nick Gasson 624943b3ca Simplify port map generation code 2008-07-01 10:59:31 +01:00
Nick Gasson ef89a760d6 Add vhdl_element::print method for debugging 2008-07-01 10:44:20 +01:00
Nick Gasson 050aa277ae Make vhdl_element::emit a little more generic 2008-07-01 10:37:22 +01:00
Nick Gasson f03dfb50ad Refactor nexus_to_var_ref 2008-07-01 10:33:46 +01:00
Nick Gasson 6e8474f584 Fix bug where func had to be declared before use 2008-06-30 17:58:15 +01:00
Nick Gasson 4e73b1b133 Fix bug when resolving nexus to VHDL signal 2008-06-30 17:47:45 +01:00
Nick Gasson e08e29c8b4 Add UFUNC LPM type 2008-06-30 16:35:29 +01:00
Nick Gasson b82ca28190 Add XOR logic type and fix part select 2008-06-30 16:18:55 +01:00
Nick Gasson 081f397460 Implement LPM part select 2008-06-27 14:58:03 +01:00
Nick Gasson f800298d01 Fix memory leak 2008-06-27 12:29:50 +01:00
Nick Gasson 301a25303f Remove useless assertion 2008-06-27 12:21:53 +01:00
Nick Gasson b24eb6ce88 Handle local variables in functions 2008-06-27 12:21:27 +01:00
Nick Gasson fd60bfd3d2 Rewrite function parameter finding code 2008-06-27 12:18:39 +01:00
Nick Gasson 500442e5c5 Working function calls 2008-06-25 22:15:57 +01:00
Nick Gasson 2baf31dff8 Fix bug with $display and integer literals 2008-06-25 21:54:11 +01:00
Nick Gasson d997397c38 Generate function calls with parameters 2008-06-25 21:49:22 +01:00
Nick Gasson 7773000c36 Generate function declarations 2008-06-25 21:40:35 +01:00
Nick Gasson 042f7ccbcd Generate a return type for functions 2008-06-25 18:43:50 +01:00
Nick Gasson 44aa8a6b91 Associate signals with scopes rather than entities 2008-06-25 18:12:57 +01:00
Nick Gasson 43c671cb5c Emit VHDL for function declarations 2008-06-25 18:00:48 +01:00
Nick Gasson a3df37b851 Initial code to generate function calls 
Also catch a few null-pointer issues
 2008-06-25 17:29:09 +01:00
Nick Gasson c01c2bd742 Dummy code for handling function scopes 2008-06-25 12:48:46 +01:00
Nick Gasson 899a70908e Fix small bug with initialisation and ammend comments 2008-06-24 20:13:18 +01:00
Nick Gasson bf95d77562 Finish replacing vhdl_process with vhdl_procedural 2008-06-24 20:01:06 +01:00
Nick Gasson db992e808f Start using vhdl_procedural instead of vhdl_process 2008-06-24 19:54:22 +01:00
Nick Gasson f2aca68b82 Add new vhdl_procedural superclass for process/task/func 2008-06-24 19:50:57 +01:00
Nick Gasson 12b448ef01 Merge branch 'vhdl' of git@github.com:nickg/iverilog into vhdl 
Conflicts:

	tgt-vhdl/vhdl_syntax.cc
 2008-06-24 19:42:35 +01:00
Nick Gasson e77bb0157e Remove redundant methods from vhdl_arch 2008-06-24 19:39:05 +01:00
Nick Gasson 75631bd8f1 Move is_inital code out of vhdl_process into vhdl_scope 
Part of tidy up before implementing functions
 2008-06-24 19:06:06 +01:00
Nick Gasson 63b1887ff2 Refactor code to use the new vhdl_scope class 2008-06-24 18:52:25 +01:00
Nick Gasson ba36e47575 Add new vhdl_scope class and refactor 2008-06-24 18:12:00 +01:00
Nick Gasson 3866c4526e Simplify code to emit operators 2008-06-24 14:58:58 +01:00
Nick Gasson cb08f02de1 Resize signed/unsigned bit vectors correctly 2008-06-24 10:58:21 +01:00
Nick Gasson 4188fbecee Add XOR operator and catch default case branch 2008-06-24 10:55:45 +01:00
Nick Gasson f261bf7e97 Fix bug where variables could be declared twice 2008-06-23 15:13:10 +01:00
Nick Gasson 88dc9b6b63 Remove debugging information from the output 2008-06-23 15:02:26 +01:00
Nick Gasson 632a265e14 Fix casting/resizing order bug 2008-06-23 15:00:55 +01:00
Nick Gasson 449cd0a76e Correctly generate signed/unsigned types 2008-06-23 14:28:27 +01:00
Nick Gasson 181a53d3ed Merge branch 'master' of git://github.com/steveicarus/iverilog into vhdl 2008-06-23 13:48:56 +01:00
Nick Gasson 44958409f5 A slightly smarter $display 2008-06-23 13:45:24 +01:00
Nick Gasson f81129aa68 Fix some bugs with blocking assignment 2008-06-23 13:36:28 +01:00
Nick Gasson e5ef0d97bd Fix signed/unsigned resizing 2008-06-23 13:04:28 +01:00
Nick Gasson 469036990a Output blocking assignments in the right place 2008-06-23 12:30:48 +01:00