Nick Gasson
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96d32b29c9
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Translate logical expressions correctly.
For logical AND/OR in VHDL both operands must be of the
same type (Boolean)
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2008-07-04 11:23:32 +01:00 |
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Nick Gasson
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c54b36c902
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Add logical AND operator
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2008-07-04 11:10:20 +01:00 |
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Nick Gasson
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6e8474f584
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Fix bug where func had to be declared before use
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2008-06-30 17:58:15 +01:00 |
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Nick Gasson
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d997397c38
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Generate function calls with parameters
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2008-06-25 21:49:22 +01:00 |
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Nick Gasson
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44aa8a6b91
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Associate signals with scopes rather than entities
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2008-06-25 18:12:57 +01:00 |
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Nick Gasson
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a3df37b851
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Initial code to generate function calls
Also catch a few null-pointer issues
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2008-06-25 17:29:09 +01:00 |
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Nick Gasson
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e77bb0157e
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Remove redundant methods from vhdl_arch
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2008-06-24 19:39:05 +01:00 |
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Nick Gasson
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4188fbecee
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Add XOR operator and catch default case branch
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2008-06-24 10:55:45 +01:00 |
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Nick Gasson
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88dc9b6b63
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Remove debugging information from the output
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2008-06-23 15:02:26 +01:00 |
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Nick Gasson
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449cd0a76e
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Correctly generate signed/unsigned types
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2008-06-23 14:28:27 +01:00 |
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Nick Gasson
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e5ef0d97bd
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Fix signed/unsigned resizing
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2008-06-23 13:04:28 +01:00 |
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Nick Gasson
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9911939576
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Simplify casting code
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2008-06-23 12:21:10 +01:00 |
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Nick Gasson
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c9ace14c40
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Shift operators working correctly
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2008-06-23 12:14:12 +01:00 |
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Nick Gasson
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c70fb4ba08
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Simple implementation of IVL_EX_SELECT
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2008-06-21 16:17:44 +01:00 |
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Nick Gasson
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7cba9f3cb2
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Shift left/right
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2008-06-21 15:19:33 +01:00 |
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Nick Gasson
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d6acb8d059
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Less than / greater than
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2008-06-21 15:16:22 +01:00 |
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Nick Gasson
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58f2f5007d
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Bitwise AND
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2008-06-21 15:05:48 +01:00 |
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Nick Gasson
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0caf4fd9d0
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Add case statement
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2008-06-21 15:03:36 +01:00 |
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Nick Gasson
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6622b5fe3a
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Compare logic values for === and !==
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2008-06-19 16:08:33 +01:00 |
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Nick Gasson
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fb31a88c51
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Blocking assignment nearly working
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2008-06-18 13:30:19 +01:00 |
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Nick Gasson
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ce72eb4eb4
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Fix Valgrind warnings
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2008-06-16 14:26:38 +01:00 |
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Nick Gasson
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7cde5f247e
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Add translation for not-equals operator
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2008-06-16 12:47:41 +01:00 |
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Nick Gasson
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849e7cb4d5
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Add equality operator
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2008-06-16 12:20:28 +01:00 |
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Nick Gasson
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8a9486eb49
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Eliminate useless Resize() call
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2008-06-14 18:11:10 +01:00 |
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Nick Gasson
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2fb57805ea
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Use signed rather than std_logic_vector
Arithmetic operators now working correctly
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2008-06-14 18:03:25 +01:00 |
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Nick Gasson
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919c1d695c
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Adding binary +
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2008-06-14 17:09:31 +01:00 |
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Nick Gasson
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005df31a0d
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Use renamed signal in expressions, if there is one
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2008-06-13 12:39:18 +01:00 |
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Nick Gasson
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645ee2003f
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Translation for unary not
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2008-06-12 10:56:28 +01:00 |
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Nick Gasson
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46991aa65c
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Generate process bodies in the right place
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2008-06-12 10:47:52 +01:00 |
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Nick Gasson
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110a1b2ac7
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Replace type classes with enumeration
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2008-06-08 12:48:56 +01:00 |
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Nick Gasson
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fbf85398da
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Support converting bit strings to std_logic
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2008-06-07 16:19:10 +01:00 |
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Nick Gasson
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cdb180e1d4
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Associate a type with each VHDL expression node
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2008-06-07 13:23:21 +01:00 |
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Nick Gasson
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305f448d05
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Generate code for signal references
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2008-06-07 11:24:09 +01:00 |
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Nick Gasson
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6e448da90d
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Emit Write() calls for parameters of $display
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2008-06-04 15:19:44 +01:00 |
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Nick Gasson
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9f035108e1
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Stub code for translating expressions
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2008-06-04 14:59:04 +01:00 |