Commit Graph

123 Commits

Author SHA1 Message Date
Larry Doolittle 9b640f3114 Shadow reduction part 4
Continue cleaning up shadowed variables, flagged by turning on -Wshadow.
No intended change in functionality.  This patch set covers the tgt-vhdl
directory, and was tested by Nick.
2008-10-30 21:46:44 -07:00
Nick Gasson 8a3309d79d Add a comment to the output about casex/z translation 2008-10-14 20:21:19 +01:00
Nick Gasson a47b7352b4 Add casex/z support
A casex statement cannot be directly translated to a VHDL case
statement as VHDL does not treat the don't-care bit as special.
The solution here is to generate an if statement from the casex
which compares only the non-don't-care bit positions.
2008-10-14 20:16:10 +01:00
Nick Gasson 4394aff909 Merge branch 'master' of git://icarus.com/~steve-icarus/verilog into vhdl
Conflicts:

	tgt-vhdl/stmt.cc
2008-10-05 12:44:30 +01:00
Larry Doolittle f233793061 Spelling fixes
No code changes.
2008-09-09 19:21:42 -07:00
Nick Gasson ec2511da64 Use British spelling and fix a few typos 2008-09-09 19:57:32 +01:00
Nick Gasson 6fe7583784 Cary R.'s additional system functions, real value error messages, etc.
I've changed the find_entity() error messages to asserts since
this should be fixed by the previous patch.
2008-09-06 12:06:01 +01:00
Nick Gasson 331a51e842 Add more warnings about untranslatable constructs 2008-08-22 20:25:58 +01:00
Nick Gasson 4ebe09bb72 Various fixes to support automatic functions
Mostly this ensures that a recursive call to a function
is made with the correct types (this may involve generating
code to cast expressions to the correct type).
2008-08-20 22:54:53 +01:00
Nick Gasson 86661c1538 Add a few more `unsupported' messages 2008-08-18 15:29:30 +01:00
Nick Gasson e2dd7425bd Add error messages for unsupported statement types 2008-08-18 15:24:38 +01:00
Nick Gasson dea54df71b Catch possibly NULL return value
This is caused by using a hierarchical reference (which can't
be translated to VHDL). The result of get_decl is NULL since
the signal has been declared in a different VHDL architecture.
Adding the assert is cleaner than having it segfault, for the
moment, until a nicer error message can be added.
2008-08-12 09:47:03 +01:00
Nick Gasson eef1c968dc Add message that casex cannot be translated
...with the correct behavior. It would be possible to
just translate it as a regular VHDL case statement (as
it was before this patch). But the behavior is not
correct as VHDL only does the equivalent of case-equality
in case statements and this can be confusing when debugging
the output. An alternative might be to emit a warning rather
than an error.
2008-08-08 20:09:40 +01:00
Nick Gasson 6f5f700cb9 Very minimal implementation of tasks
This expands the task in-line inside the process to avoid
problems with global variables (VHDL processes cannot
reference globals)
2008-08-07 10:54:39 +01:00
Nick Gasson f86f454956 Apply the last patch to if/case statements too
This further cleans up the output by removing more
useless `wait for 0ns' statements.
2008-08-05 11:09:51 +01:00
Nick Gasson e01e038cf9 Avoid generating useless `wait for 0ns' statements
If the final statement in a process is a non-blocking
assignment then there is no point adding a `wait for 0ns'
after it since it will be immediately followed by another
wait. This case is suprisingly common, so this patch helps
generate much cleaner output without breaking the cases
where the 0ns wait is actually required (e.g. to implement
non-blocking assignment properly).
2008-08-05 11:02:36 +01:00
Nick Gasson 72019959a8 Translate some ternary expressions to if statements
This re-implements some earlier functionality where
ternary expressions on an assignment RHS are translated
to an if statement.
2008-08-03 15:47:32 +01:00
Nick Gasson c1b5424ca6 Implement assignment with multiple lvals
Multiple lvals are implemented by first assigning the complete
RHS to a temporary, and then assigning each lval in turn as
bit-selects of the temporary
2008-08-02 18:40:24 +01:00
Nick Gasson c706c94e38 Generate a vhdl_var_ref for every assignment lval
This completes the refactoring of make_assignment
necessary to implement multiple lvals.
2008-08-02 18:20:18 +01:00
Nick Gasson fad8abee34 Start refactoring make_assignment for multiple lvals
This patch lifts the RHS generating code out of the
lval-specific code and sticks a loop around the lvals.
2008-08-02 16:38:44 +01:00
Nick Gasson 9448c5939c Always user Ternary_* support functions for ternary assignments
Previously the code generator expanded ternary assignments to
and `if' statement. This patch replaces that with a single assignment
and a call to a Ternary_* support function. This will make it
much easier to support multiple lvals later.
2008-08-02 15:46:36 +01:00
Nick Gasson 8b32096e2a Convert std_logic to Boolean in loop tests 2008-07-27 18:39:16 +01:00
Nick Gasson 39c9c54760 Add repeat statement 2008-07-24 14:52:06 +01:00
Nick Gasson 8bee5b1108 Add `forever' statement type 2008-07-24 14:30:10 +01:00
Nick Gasson e4c2400eb2 Refactor the expression->time code into a single function 2008-07-23 16:18:49 +01:00
Nick Gasson 7b311b6adb Translate internal delays in assignments 2008-07-18 14:47:35 +01:00
Nick Gasson e9637f6d11 Generate synthesisable code for sequential processes
Whilst adding `wait until ...' at the end of every
process is a valid translation of the input, it is not
actually synthesisable in at least one commercial
synthesiser (XST). According to the XST manual the
correct template is to use `wait until ...' at the
start of sequential processes and `wait on ...'
(equivalent to `wait until ...' with 'Event on all
the signals) at the end of combinatorial processes.
This patch implements that.
2008-07-17 17:36:42 +01:00
Nick Gasson 1f9ed2c5ec VHDL AST element for `wait on' statement 2008-07-17 17:23:21 +01:00
Nick Gasson 2a791bfb38 Assignment to arrays 2008-07-17 13:41:44 +01:00
Nick Gasson be67cae29f Add translation for IVL_ST_CASEX 2008-07-16 16:42:44 +01:00
Nick Gasson 4504c2bceb Fix initialisation order bug with `if' statements
If an assignment appears inside an if statement branch
it could be incorrectly used as the signal's initial
value.
2008-07-16 12:11:00 +01:00
Nick Gasson b5e12077b2 Fix assignment to lval slice
It was broken in yeserday's refactoring
2008-07-15 18:40:30 +01:00
Nick Gasson a9c98ad5f2 Handle `if' with empty cond_true part
Fixes assertion failure with following statement:

if (foo)
  begin
  end
else
  ...
2008-07-15 14:26:19 +01:00
Nick Gasson b8e758edf0 Refactor LPM code 2008-07-15 14:09:24 +01:00
Nick Gasson 0b48f69b4e Tidy up blocking assignment code 2008-07-15 10:44:48 +01:00
Nick Gasson d1e7e325b7 Remove redundant edge_detector function 2008-07-14 21:34:48 +01:00
Nick Gasson 75b1db0add Fix assignment with ternary RHS
This was also broken in the last commit
2008-07-14 21:27:21 +01:00
Nick Gasson 6e965523a1 Fix PV assignment (was broken in last commit) 2008-07-14 21:09:19 +01:00
Nick Gasson 8589c0691b Refactor assignment code 2008-07-14 21:04:09 +01:00
Nick Gasson 99ef8ec4f1 Simplify edge detector code
Now generates a `wait until' statement rather than a
sensitivity list.
2008-07-14 20:29:49 +01:00
Nick Gasson d22c9a8b05 Simplify blocking assignment
Now generates 'wait for 0 ns' after non-blocking assignment
2008-07-14 19:54:45 +01:00
Nick Gasson 4777966b4c Bit select bug fixes 2008-07-07 21:19:59 +01:00
Nick Gasson 0348664512 Correctly determine VHDL type of LHS of part select 2008-07-07 16:35:39 +01:00
Nick Gasson b0de1a8d7e Implement part select for LHS of assignment 2008-07-07 16:11:45 +01:00
Nick Gasson bdf5ee7ab7 Concat LPM 2008-07-07 14:48:57 +01:00
Nick Gasson ebaa4c7d5d Implement assignment to part select properly
Previously the base of the lval was ignored, this ensures
the correct assignment is generated.
2008-07-07 11:00:27 +01:00
Nick Gasson 85d2cc78d6 Finish ternary operator expansion 2008-07-06 17:56:48 +01:00
Nick Gasson 18071562ba Partially implement ternary expressions
This handles the case where the expression appears as the
right hand side of an assignment. The expression is converted
into a regular if statement.
2008-07-04 21:55:51 +01:00
Nick Gasson 5aeff6d47d Merge blocking and non-blocking assignment code 2008-07-04 20:07:38 +01:00
Nick Gasson 19871efd5a Fix bug where sensitivity might reference undefined signals 2008-07-04 11:58:33 +01:00