AngeloJacobo
|
1078e2ffe0
|
Revert "add self-refresh option, passing Simulation, ongoing formal"
This reverts commit a5e2adf4a4.
|
2024-11-23 11:43:05 +08:00 |
|
AngeloJacobo
|
a5e2adf4a4
|
add self-refresh option, passing Simulation, ongoing formal
|
2024-11-17 20:47:14 +08:00 |
|
AngeloJacobo
|
c58a9d70e6
|
add self-refresh feature (untested)
|
2024-11-03 14:52:32 +08:00 |
|
AngeloJacobo
|
65bcf2f621
|
add option to skip internal test for Microblaze use
|
2024-10-26 09:07:24 +08:00 |
|
AngeloJacobo
|
e89b06defd
|
paremeterized IOSERDES loopback option
|
2024-10-13 16:42:31 +08:00 |
|
Angelo Jacobo
|
95820556c2
|
replace ioserdes loopback with logic
|
2024-10-12 09:43:27 +08:00 |
|
Angelo Jacobo
|
aa68c22169
|
turn off ECC test by default
|
2024-09-01 09:04:45 +08:00 |
|
AngeloJacobo
|
fc963c3c23
|
simulation and formal are now passing for all ECC types
|
2024-07-28 17:36:37 +08:00 |
|
AngeloJacobo
|
f80d4ac21b
|
simulation passing for ECC_ENABLE = 3
|
2024-07-15 18:31:49 +08:00 |
|
AngeloJacobo
|
de85925681
|
add support for ECC_ENABLE = 3
|
2024-07-06 21:24:01 +08:00 |
|
AngeloJacobo
|
71b0383cda
|
add support for other memory address mapping (row_bank_col = 0,1, or 2)
|
2024-07-06 09:01:34 +08:00 |
|
AngeloJacobo
|
c81c51c9f4
|
add support for ECC = 1 and 2, passing simulation and formal verification
|
2024-06-29 19:36:01 +08:00 |
|
AngeloJacobo
|
f2805d0e90
|
resolve verilator lint flags
|
2024-06-24 17:16:26 +08:00 |
|
AngeloJacobo
|
7d93717b72
|
add initial ECC, ECC_ENABLE = 2 working
|
2024-06-17 16:25:06 +08:00 |
|
AngeloJacobo
|
0ca641799d
|
add bit files for example demo
|
2024-06-10 16:44:41 +08:00 |
|
AngeloJacobo
|
8fb24dd180
|
add copyright on headers
|
2024-06-09 12:01:30 +08:00 |
|
AngeloJacobo
|
2333095668
|
clean repo
|
2024-06-09 11:31:58 +08:00 |
|
Angelo Jacobo
|
1ce369cc1f
|
Merge pull request #6 from AngeloJacobo/kimos_dev
add support for kimos project
|
2024-06-09 10:52:18 +08:00 |
|
AngeloJacobo
|
a1b15fb9d6
|
elevate DIC and RTT_NOM as parameters
|
2024-06-09 10:50:18 +08:00 |
|
Angelo Jacobo
|
df776e059a
|
Merge pull request #5 from AngeloJacobo/new_feature_axi
added AXI4 interface option on top of current wishbone interface
|
2024-06-03 17:41:45 +08:00 |
|
AngeloJacobo
|
91fc6d8ed6
|
moved axi-related files to separate folders
|
2024-06-03 17:36:19 +08:00 |
|
AngeloJacobo
|
593f56ac4a
|
resolve warning in implementation: not connected to load
|
2024-06-02 19:20:10 +08:00 |
|
AngeloJacobo
|
9c440d535f
|
fix bug in write levelling with cntvalue > 15 (reaches 31), changed mark_debug for debugging
|
2024-06-02 19:19:17 +08:00 |
|
AngeloJacobo
|
66f0daf0e9
|
added AXI4 feature
|
2024-06-01 15:30:15 +08:00 |
|
AngeloJacobo
|
a6982da97d
|
match dic and rtt_nom settings
|
2024-05-26 20:53:00 +08:00 |
|
AngeloJacobo
|
eaa45f01d5
|
fix error in formal verif
|
2024-05-26 20:27:53 +08:00 |
|
AngeloJacobo
|
57aebc6eef
|
fixed error in slot calculation
|
2024-05-25 13:49:48 +08:00 |
|
AngeloJacobo
|
18283f4436
|
clean verilator lint by making parameters integer (instead of being inferred as real)
|
2024-05-24 22:43:34 +08:00 |
|
AngeloJacobo
|
88a913f8da
|
clean verilator lint
|
2024-05-24 21:51:20 +08:00 |
|
AngeloJacobo
|
237752fa3d
|
clean printed details
|
2024-05-06 17:11:04 +08:00 |
|
AngeloJacobo
|
1d1fd96893
|
fixed bug when READ_SLOT and WRITE_SLOT is the same
|
2024-05-05 21:15:02 +08:00 |
|
AngeloJacobo
|
22f6db696c
|
automatically generate CL and CWL value based on ddr3 clock period
|
2024-05-05 15:21:55 +08:00 |
|
AngeloJacobo
|
bb26b0ef4c
|
fixed BYTE_LANES
|
2024-05-05 14:03:51 +08:00 |
|
AngeloJacobo
|
81a6ab32f9
|
removed OPT parameters (no use), and add defines
|
2024-05-05 13:32:37 +08:00 |
|
Angelo Jacobo
|
e9633ddae7
|
fixed instantiation template
|
2024-05-05 13:27:51 +08:00 |
|
Angelo Jacobo
|
da8eaa5d91
|
make internal test shorter during sim
|
2024-04-21 13:06:19 +08:00 |
|
Angelo Jacobo
|
81865ea2f8
|
make controller not dependent on chip-select cs_n
|
2024-04-20 15:03:47 +08:00 |
|
Angelo Jacobo
|
25685e5769
|
make internal test shorter during simulation
|
2024-04-20 12:24:49 +08:00 |
|
Angelo Jacobo
|
be88286891
|
fixed rtoi error in vivado
|
2024-04-20 12:20:50 +08:00 |
|
Angelo Jacobo
|
d489b867d7
|
fixed rtoi error in vivado
|
2024-04-20 12:20:20 +08:00 |
|
Angelo Jacobo
|
31f02da699
|
fixed rtoi error from vivado and add more options for speedbin and capacity
|
2024-04-20 12:18:04 +08:00 |
|
Angelo Jacobo
|
eb5774d518
|
add more comments
|
2024-03-28 14:59:56 +08:00 |
|
Angelo Jacobo
|
b308e507d1
|
add more comments
|
2024-03-28 14:21:16 +08:00 |
|
Angelo Jacobo
|
117a6dbdec
|
add more comments
|
2024-03-28 14:19:00 +08:00 |
|
Angelo Jacobo
|
21a35d4c49
|
add more comments
|
2024-03-28 14:05:46 +08:00 |
|
Angelo Jacobo
|
94c801990e
|
add more comments
|
2024-03-27 20:03:12 +08:00 |
|
Angelo Jacobo
|
a0fb015059
|
add more comments
|
2024-03-27 18:59:53 +08:00 |
|
Angelo Jacobo
|
4e16cac338
|
add more comments
|
2024-03-26 07:43:51 +08:00 |
|
Angelo Jacobo
|
3bafed0015
|
add more comments
|
2024-03-25 21:21:01 +08:00 |
|
Angelo Jacobo
|
4f73cf0a7a
|
add more comments
|
2024-03-24 15:05:14 +08:00 |
|
Angelo Jacobo
|
775a9ad1fe
|
add more comments
|
2024-03-24 13:39:29 +08:00 |
|
Angelo Jacobo
|
4e557d795b
|
add more comments
|
2024-03-23 11:48:01 +08:00 |
|
Angelo Jacobo
|
2c560b65ba
|
add more comments
|
2024-03-23 11:05:00 +08:00 |
|
Angelo Jacobo
|
910a4d00a3
|
add more comments
|
2024-03-23 08:42:22 +08:00 |
|
Angelo Jacobo
|
22bd2f1118
|
add more comments
|
2024-03-22 19:50:14 +08:00 |
|
Angelo Jacobo
|
cf3bc8c629
|
added more comments
|
2024-03-22 18:30:51 +08:00 |
|
AngeloJacobo
|
9a88f5540c
|
fix displayed report
|
2023-11-26 13:21:15 +08:00 |
|
AngeloJacobo
|
efc194a633
|
add instantiation template
|
2023-11-18 13:35:38 +08:00 |
|
AngeloJacobo
|
292f94c530
|
make 2nd wishbone removable via cyc line
|
2023-11-18 13:34:27 +08:00 |
|
AngeloJacobo
|
c2fc70fb6c
|
changed to picosecond-based instead of nanoseconds
|
2023-11-14 14:14:16 +08:00 |
|
AngeloJacobo
|
29ec2d0714
|
changed to picosecond-based instead of nanoseconds
|
2023-11-14 14:13:41 +08:00 |
|
AngeloJacobo
|
c514d492f1
|
changed to picosecond-based instead of nanoseconds
|
2023-11-14 14:11:40 +08:00 |
|
AngeloJacobo
|
0cfd8243ab
|
remove all IODELAY_GROUP lines
|
2023-11-11 11:32:14 +08:00 |
|
AngeloJacobo
|
33ec101b79
|
resolve bug "Conflicting initialization values for \index"
|
2023-11-11 10:18:15 +08:00 |
|
AngeloJacobo
|
896d3f4f23
|
clean description,and added missing parameters
|
2023-11-09 13:49:41 +08:00 |
|
AngeloJacobo
|
20953ee65f
|
fixed bug when ODELAY is not supported, clean file header and description
|
2023-11-09 13:25:39 +08:00 |
|
AngeloJacobo
|
a80bacb718
|
add reset control from controller to phy
|
2023-09-15 19:59:39 +08:00 |
|
AngeloJacobo
|
922d185643
|
now passes internal test calibration on klusterboard
|
2023-09-15 19:58:36 +08:00 |
|
AngeloJacobo
|
8c5c5e30cc
|
now passes internal test calibration on klusterboard
|
2023-09-15 19:58:12 +08:00 |
|
AngeloJacobo
|
20db6352e2
|
added write read test after calibration
|
2023-09-08 17:15:34 +08:00 |
|
AngeloJacobo
|
de4fb994b4
|
add debug lines and update wb2 registers
|
2023-09-05 20:17:10 +08:00 |
|
AngeloJacobo
|
92c25f394f
|
add wire for cue when write leveling starts
|
2023-09-05 18:33:20 +08:00 |
|
AngeloJacobo
|
2ee7e35bc5
|
add dci reset and optional DCIEN IO buffers
|
2023-09-05 18:32:30 +08:00 |
|
AngeloJacobo
|
03a1da2ce7
|
add calibration when DQS toggles early than DQ
|
2023-09-05 18:31:10 +08:00 |
|
AngeloJacobo
|
8f3d673e3d
|
fixed bug when issue write calibration has to be repeated
|
2023-08-22 16:40:44 +08:00 |
|
AngeloJacobo
|
83b7b95af4
|
pass verilator warning
|
2023-08-20 12:32:51 +08:00 |
|
AngeloJacobo
|
e2653d5793
|
reset for IO is released only after IDELAYCTRL is ready, added also IODELAY_GROUP
|
2023-08-20 11:09:38 +08:00 |
|
AngeloJacobo
|
9769a7cfaa
|
pass formal for 8-lane config and pass verilator linting
|
2023-08-20 11:07:22 +08:00 |
|
AngeloJacobo
|
36c93689e5
|
redo read/write calibration if data read is wrong
|
2023-08-17 11:27:23 +08:00 |
|
AngeloJacobo
|
f296d08c6b
|
add option for ODELAY_SUPPORTED=0 and added port for i_ddr3_clk_90
|
2023-08-15 19:37:28 +08:00 |
|
AngeloJacobo
|
411febc1a8
|
add option for ODELAY_SUPPORTED=0 (for FPGAs without ODELAY)
|
2023-08-15 19:35:44 +08:00 |
|
AngeloJacobo
|
b3ab21a6d5
|
add option for ODELAY_SUPPORTED=0 (for FPGAs without ODELAY)
|
2023-08-15 19:12:49 +08:00 |
|
AngeloJacobo
|
e9f1ab4971
|
modify debug port logic for wbscope
|
2023-08-04 07:57:09 +08:00 |
|
AngeloJacobo
|
0753e6e157
|
fixed localparam value for wb_addr_bits
|
2023-08-04 07:53:12 +08:00 |
|
AngeloJacobo
|
72dc00742b
|
correct generate indexes
|
2023-08-04 07:52:31 +08:00 |
|
AngeloJacobo
|
1bfd851a6e
|
pass formal with LANES either 1,2,4,8
|
2023-08-04 07:49:25 +08:00 |
|
AngeloJacobo
|
2c73f38f99
|
added debug port and max function for int type
|
2023-08-01 15:58:58 +08:00 |
|
AngeloJacobo
|
d5f1d600ea
|
resolve verilator warnings and add option YOSYS for not using input real in functions
|
2023-07-24 17:27:17 +08:00 |
|
AngeloJacobo
|
60e40f9d35
|
less simulation warning
|
2023-07-19 18:48:31 +08:00 |
|
AngeloJacobo
|
e38859ef78
|
resolved warning from vivado on IOBDELAY
|
2023-07-19 18:47:24 +08:00 |
|
AngeloJacobo
|
7142dd9cdb
|
added more registers and formal assertions to wb2
|
2023-07-19 18:46:36 +08:00 |
|
AngeloJacobo
|
137e30ba36
|
resolve vivado warnings
|
2023-07-17 21:39:07 +08:00 |
|
AngeloJacobo
|
97e740139f
|
resolved vivado warnings
|
2023-07-17 21:38:20 +08:00 |
|
AngeloJacobo
|
983919d9df
|
removed unneeded .* files
|
2023-07-16 08:52:10 +08:00 |
|
AngeloJacobo
|
4f857e08f4
|
add files back after git rm -r cached .
|
2023-07-16 08:46:16 +08:00 |
|
AngeloJacobo
|
b16c4d56cd
|
fixed error due to missing port dm and incorrect IO type for aux
|
2023-07-16 08:39:24 +08:00 |
|
AngeloJacobo
|
b80bda4a46
|
resolve warning from verilator linting
|
2023-07-16 08:38:20 +08:00 |
|
AngeloJacobo
|
019722bc70
|
resolve warnings and errors from verilator linting
|
2023-07-16 08:17:55 +08:00 |
|
AngeloJacobo
|
ee83028986
|
make stall and accessible outside, removed added assumptions with i_slave_busy
|
2023-07-13 18:48:34 +08:00 |
|
AngeloJacobo
|
2541d0afcc
|
added wishbone 2 ports
|
2023-07-13 18:45:43 +08:00 |